MIZAN TEPI UNIVERSITY

COLLEGE OF ENGINNERING AND TECHNOLOGY

DEPARTMENT OF ELECTRICA AND COMPUTER ENGINEERING

CAO [ECEG 3143] 1 to 5 group Assignment for 3rd YEAR STUDENTS

APRIL 10, 2021

For Group: ONE (1) and TWO (2)

INSTRACTIONS
i. Look the table below and select the questions that are
assigned based on your sub group.
ii. Clearly show each and every answers with justifications.
iii. Maximum wait (15%)
iv. Submission date (April 17, 2021) @ Sat 3:15 LT

Assignment questions for group one and group two

Group 1 Group 2
Sub group Assigned Question number Sub group Assigned Question number
Sub group1 Q1,Q11,Q21,Q31,Q41,Q51 Sub group1 Q2,Q12,Q22,Q32,Q42,Q52
Sub group2 Q3,Q13,Q23,Q33,Q43,Q53 Sub group2 Q4,Q14,Q24,Q34,Q44,Q54
Sub group3 Q5,Q15,Q25,Q35,Q45,Q55 Sub group3 Q6,Q16,Q26,Q36,Q46,Q56
Sub group4 Q7,Q17,Q27,Q37,Q47,Q57 Sub group4 Q8,Q18,Q28,Q38,Q48,Q58
Sub group5 Q9,Q19,Q29,Q39,Q49,Q59 Sub group5 Q10,Q20,Q30,Q40,Q50,Q60
Sub group6 Q61,Q63,Q65,Q67,Q69,Q71 Sub group6 Q62,Q64,Q66,Q68,Q70,Q72

1. What is the concept of layers in architectural design?

2. Write typical physical realizations of architecture and explain the significance of layered
architecture.
3. Explain the various types of performance metrics and How can you evaluate the performance
of processor architecture?

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4. Write a short note on “cost/benefit in layered Architecture design.” Or H/W and S/W
partitioning design:
5. What is principle of performance and scalability in Computer Architecture and what is
evaluation of computer architecture?
6. What is parallelism and pipelining in computer Architecture?
7. What is cost/benefit in layered Architecture design? Or Write functional view of computer
which are the possible computer operational.
8. List and briefly define the main structural components of a computer also List and briefly
define the main structural components of a processor.
9. What has been the trend in computing from the following points of view?
(a) Cost of hardware. (b) Size of memory. (c) Speed of hardware. (d) Number of processing
elements. (e) Geographical locations of system components.
10. Briefly explain about Embedded Systems – Architecture with design and detail example.
11. Explain about Compilers and Assemblers, also when we use compilers and assemblers?
12. Distinguish between computer architecture and computer organization and also explain
structure and function.
13. How many cycles are required to execute per instruction for 8086, 8088, Intel 286, 386, 486,
Pentium, K6 series, Pentium 11/111/4/cebron and Athion/Athion XP/Duron?
14. You are required to write a program segment that can perform the operation C A+B
where each of A and B represents a set of 100 memory locations each storing a value such that
the set of values represented by A are stored starting at memory location 1000 and those
represented by B are stored starting at memory location 2000. The results should be stored
starting at memory location 3000. The above operation is to be performed using each of the
following instruction classes.
(a) A machine with one-address instructions
(b) A machine with one-and-half instructions
(c) A machine with two-address instructions
(d) A machine with three-address instructions
(e) A machine with zero-address instructions

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15. Register A holds the 8-bit binary 11011001. Determine the B operand and the logic micro
operation to be performed in order to change the value in A to:
A) 01101101 B) 11111111
16. An 8-bit register R contain the binary value 10011100 what is the register value after an
arithmetic shift right? Starting from the initial number 10011100, determine the register value
after an arithmetic shift left, and state whether there is an overflow.
17. A computer system has an MM consisting of 16 MB 32-bit words. It also has
an 8 KB cache. Assume that the computer uses a byte-addressable mechanism. Determine the
number of bits in each field of the address in each of the following organizations:
(a) Direct mapping with block size of one word.
(b) Direct mapping with a block size of eight words.
(c) Associative mapping with a block size of eight words.
(d) Set-associative mapping with a set size of four block and a block size of one word.

18. Design a 4-bit common bus to transfer the contents of one register to other.
19. Briefly explain instruction format.
20. What is instruction pipelining?
21. Explain micro programmed control.
22. Explain pipelining in CPU design?
23. Explain basic six important features of RISC based on system architecture.
24. How pipelining would improve the performance of CPU justify.
25. Give the comparison between and examples of hardwired control unit and micro programmed
control unit.
26. What do you understand by Fetch cycle, instruction cycle, machine cycle, inter-put
acknowledgment?
27. Compare the instruction set Architecture is RISC and CISC processor in the instruction
formats, addressing modes and cycle per instruction (CPI).
28. What cause of processor pipeline to be under pipelined?
29. Write short note on Hazards of pipelining.
30. What are reasons of pipeline conflicts in pipelined processor? How are they resolved?

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31. Explain instruction set of SPARC with description.
32. What do you mean by software and Hardware interrupts? How these are used in
microprocessor.
33. What do you mean by memory hierarchy? Briefly discuss.
34. How many memory chips of (128x8) are needed to provide memory capacity of 4096 x 16?
35. Differentiate among direct mapping and associate mapping.
36. What shall be the range of addresses that is being used by the RAM?
37. Write about DMA transfer.
38. What is memory organization? Explain various memories?
39. Compare interrupt I/O with DMA I/O?
40. What do you mean by initialization of DMA controller? How DMA Controller works? Explain
with suitable block diagram?
41. When a DMA module takes control of bus and while it retain control of bus, what does the
processor do?
42. (a) How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes?
(b) 1How many lines of the address bus must be used to access 2048 bytes of memory? How
many these lines will be common to all chips?
(c) How many lines must be decoded for chip
select? Specify the size of decoder.
43. A computer uses RAM chips of 1024 x 1 capacity.
(a) How many chips are needed, and how should there address lines be connected to provide
a memory capacity of 1024 bytes?
(b) How many chips are needed to provide a memory capacity of 16K bytes? Explain in
words how the chips are to be connected to the address bus? Specify the size of the decoders.
44. An 8-bit computer has a 16-bit address bus. The first 15 lines of address are used to select a
bank of 32K bytes of memory. The higher order bit of address is used to select a register which
receives the contents of the data bus? Explain how this configuration can be used to
extend the memory capacity of system to eight banks of 32 K bytes each, for a total of 256
bytes of memory.

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45. The logical address space in a computer system consists of 128 segments. 'Each segment can
have up to 32 pages of 4K words in each physical memory consists of 4K blocks of 4K words
in each. Formulate the logical and physical address formats.
46. Why does increasing the capacity of cache tend to increase its hit rate?
47. Extend the memory system of 4096 bytes to 128 x 8 bytes of RAM and 512 x 8 bytes of ROM.
List the memory address map and indicate what size decoder are needed if CPU address bus
lines are 16 x 4096.
48. A computer employ RAM chips f 256 x 8 and ROM chips of 1024 x 8. The computer system
needs 2k byte of RAM, 4K bytes of ROM and four interface units, each with four register. A
memory mapped 1/0 configuration is used. The two highest order bits of the address assigned
00 for RAM, 01 for ROM, and 10 for interface registers.
(a) How many RAM and ROM chips are needed?
(b) Draw a memory-address map for the system.
49. Write major requirement for I/O module and Write characteristics of I/O channels.
50. Describe in detail the different kinds of addressing modes with an example.
51. Briefly explain the organization of ISA computer.
52. Explain in detail about CPU organization and describe about register level components.
53. Explain chip set and how it manage data between each components.
54. Explain how the control unit of the CPU interprets machine level instruction.
55. Where does the instruction cycle take place, why does data need to be fetched and isn’t it okay
where it is?
56. Explain how the computer keep track of instruction and where does the computer put the
instruction it has just fetched?
57. An array of two integers (each integer = 32 bits) is placed in memory starting with address
100. Show how to increment each element of the array using register indirect addressing mode.
58. What is basic function of interrupt controller and Write and explain all classes of interrupts.
59. What is the difference between isolated mapped I/O and memory mapped input output. What
are the advantages and disadvantages of each?
60. When a device interrupt occurs, how does the processor determine which device issued the
interrupt.

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61. Explain about parallel and distribution computers, Write and explain types of parallel processor
systems and Compare SIMD and MIMD machine.
62. What is meant by hierarchical bus system for multiprocessing system?
63.

64.

65.

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66. Determine the micro operation that wil be executed in the processor . when the following 14-
bit control word are applied.

67.

68.

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69. A computer system has a Memory Mapping (MM) consisting of 1 M 16-bit words. It also has
a 4 K word cache organized in the block-set-associative manner, with four blocks per set and
64 words per block. Assume that the cache is initially empty. Suppose that the CPU fetches
4352 words from locations 0, 1, 2... 4351 (in that order). It then repeats this fetch sequence
nine more times. If the cache is 10 times faster than the MM, estimate the improvement factor
resulting from the use of the cache. Assume that whenever a block is to be brought from the
MM and the correspondence set in the cache is full, the new block replaces the least recently
used block of this set. Repeat for the case of using the most recently used replacement
technique; that is, if the cache is full, then the new block will replace the most recently used
block in the cache.

70. Write a micro-program for the fetch instruction using the one-bus data path and the two-bus
data path.
71. Suppose that the instruction set of a machine has three instructions: Inst-1, Inst-2, and Inst-3;
and A, B, C, D, E, F, G, and H are the control lines. The following table shows the control
lines that should be activated for the three instructions at the three steps T0, T1, and T2.
Step Inst-1 Inst-2 Inst-3
T0 D, B, E F, H, G E, H
T1 C, A, H G D, A, C
T2 G, C B, C

(a) Hardwired approach:

(i) Write Boolean expressions for all the control lines A–G.
(ii) Draw the logic circuit for each control line.
(b) Microprogramming approach:
(i) Assuming a horizontal representation, write down the microprogram for
instructions Inst-1. Indicate the microinstruction size.

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 (ii) If we allow both horizontal and vertical representation, what would be the best grouping?
What is the microinstruction size? Write the microprogram of Inst-1.

72. Consider the case of a 48 two-dimensional array of numbers, Assume that each number in the
array occupies one word and that the array elements are stored row-major in the main memory
for location 1000 to location 1031. The cache consists of eight blocks each consisting of four
words. Assume also that whenever needed, LRU replacement policy is used. We would like to
examine the changes in the cache if each of the above three mapping techniques is used as the
following sequence of requests for the array elements is made:
a0,0, a0,1, a0,2, a0,3, a0,4,, a0,5, a0,6, a0,7
a1,0, a1,1, a1,2, a1,3, a1,4, a1,5, a1,6, a1,7
a2,0, a2,1, a2,2, a2,3, a2,4, a2,5, a2,6, a2,7
a3,0, a3,1, a3,2, a3,3, a3,4, a3,5, a3,6, a3,7
Show the status of the cache before and after the given requests were made, the number of
replacements made, and an estimate of the cache utilization.

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