Roll No 12001006 Paper Code ii061 NA Page No9.

Ans: Dire.ct Memors Access (DMA):

bravideS
The Direct memory Access (DMA) iS an T/o technique that
direct AGcess to the mainmemory_while CPu is temborarilu
Ldisable.d,to sheed uh the memoru 0berations-
Controller
Ihis bracess is_managed bhs a chib knoun aS DMA
LCDMAG.
I 6devices are Connecked to System Bus via a Shecial InterHace
Circuit called"DMA Controller"
In DMA,both CPU and DMA Controller have acc.ess to he main
memoru via Shared System bus having data, Address_and
Control lines.
DMA allows Tlo Devices to transter data directlu to or
ftom the main_memory with.o ut CPU intervention CorSimblu
by aSSing the CPU trom the bath
ABUS
Add ress BUS -
DBUS AR Conhol Sionals
Data BUS From To to
DS
DMA Select weR DMA Controller
RS DMA for it'S Access
Register Select
RD
Read Controller R
WR
write DMA Request
BR
BusReguest
BUs Groant BG
Lnterrust DMA Acknouwle9-
Interrubt
-ment
Control lineS fig:DMA Controller

DMA Controller takesover tht Contralof Buses to allouw the

tranSfer direcHy iom main_Me.mory to or from Ilo devices
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Roll No 12001006 Paper Code 11061/N1 Page No10.

DMA lorking:

ohen Ilo wans to transfer data with main Memory

Ilo device Sends DMA Reguest to DMA Controller (DMAC).
DMACSends BR(Bus Request) Siqnal to CPU for requesting
he conhrol ot Buses
DMA waits untilL CPU SendS BG Bus G1rant) Signal to DMA
CPU neleaSe the antrol oBuses and place Address BUS
LARUS), Dato Bus (DBUS), Read (RD) and lwrite (WR) lines
into High-Tmbedenc.e State
CPU activates the BG (Le Bus Grant) Stanal and becomes im
Idle Stote (disabled).
DMA Contmller takes Conhnl of Buses to Conduct direct
memory transfer withdut CPU InteryentHon
when DMA tanster terminates,it dis.a.bles Hhe BRG.e
Bus Request)line.
The CPU disables the BGCBUS Gant).
After that CPu toakes the Contral of BuSES and returnto
S normal oheotion.
BRRus Reauest
DMA BGRLS Girant+
I/o Acknowlegment
DMA
Requestt BR ABUS
DMA DBUS
High
Controller C.P.U RD
Tmbedence
BG Cdisobled)
wR hen BG-1
Enabled
Main CPU Signal to DMA Conttoller
Memory that Buseaare in High-Imbedence
(RAM)
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Roll No 2001006 Paper Code 1io61/NJ Page No 11

DMATransfer:
CPU via data bus_
he DMA Controller Communjcates with the
and Control line.S.
Ihe Connection between the DMA Contraller and ofher Combanen-
fallnwsi
ESina Combuter Suskem tor DMA Tansfer is as
Randam-Access
Interrupt
BG CPU Memory (RAM)
BR
RD wR Address Data. RD WR Address Data |

RD
wR
Data BUS
Address Address BUS
Select
RD WRR Address Data

DS DMA
Reques+
RS DMA Periphera
DMA Device
BR Controller
BG Acknouslege
Tnterrupt
Frg: DMA Iranster

The DMA request line is used to request a DMA Tmnster

The Registers in DMA are selectedbu the CPU through
he Address BuS by enabling DS(DMA Select) and
Register Seleck
Read (RD) and wurite LwR lines are Bidirectional
Luhen BG (Bus arant) inbut iS 0 (i:e BG=0) the CPUCa
1Communicate ith DMA Registers, hrough he Dato BUS to
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 Page No12.
Roll No 1200 1006 Paper Code11o61 NJ

read from or write to the DMA Registers.

Busts and the
hen BG: 1, the CPu has to release the
emor-
DMACan CommuniG.ate directu with fhe main
byShecifuing an address in he AddressBus
and
a.ctivating Rn and uwR Contral.
DMACo.mmumicate with the external Tlo devices through
Tne_request and ackmowlegment lines by he HandShalsiue
rocedue
he DMA Acknoulegment 1line is set when the Sysienm iS
readyto initiate data tmnsfer
he data lous is uSed to transter_clata hetween T/o device
and memoru
Lwhen the last word odata in the DMA hransfer i s
ransfer red, he dma Cont roller informs the fermmation
ohransfer to CPU bå means o Inierrukt lines
4-bute burst Burst Transfer
Modes of DMA Transter: Mode

) |Burst Transter:
Tn DMA, Burst Trans fer, Li.ea black_Seqvence_Consistingo
numberomemary wordsto ransterre.d in Gonlinuous
burst while the DMA is mast+er o memory BUSES
This mode is needed or fast devices Such aa magnelicdisk
where the data ransfer Can' be Slouwed.
Breakbotnt_
it Cacle Stealing
Caycle Sealing,allouws DMA Canhmller to tran8fer one data word
ata ime, after uhich it must rehurn Cantrol tn CPU_
The CPU_merely_delays it'S Oheratinn for one memory Cycle to
alloln the direct transfer m Ilot_ memory_ to 'steal) one
memary Cycle 18ed bu Sloo devices Such as keybnard
Debak kwmar
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