Microprocessors and

Interfacing Techniques

Lecture 13
 Review of I/O Types
1. Programmed I/O
I/O between memory and the I/O device is performed by the Processor: e.g.
IN AL,DX
MOV [DI],AL; Transfer is through the mP - slow!
1.1 Polling/Handshaking I/O
Processor checks device readiness repeatedly, e.g. in a tight loop

1.2 Interrupt-driven I/O

Device signals its readiness by an interrupt. Processor performs I/O by
executing an ISR. Otherwise processor is doing other useful work

2. Direct Memory Access (DMA)

- Avoids the slow speed of programmed I/O when moving large amounts of
data between memory and a peripheral
- Data transfer is coordinated by a DMA controller- not the processor
- Avoids the bottleneck of having to channel data through the mP
- Uses the 3 mP buses, so the mP is unable to use them temporarily
- Speed is limited only by those of the memory and the DMAC
DMA
• Direct Memory Access (DMA) is a method whereby the
memory and I/O space of the microprocessor can be
accessed directly without the intervention of the
microprocessor or a program.
• To request DMA access, the DMAC raises the HOLD input
high.
• The microprocessor responds by floating the 3 buses and
raising HLDA high to indicate that a hold is in effect.
• The DMAC can now use the 3 buses to do DMA transfers
on them- bypassing the processor
• During a HOLD, the microprocessor stops running the
program and places its address, data, and control bus
connections at their HiZ state. This in effect is the same
as removing the microprocessor from its socket!
• While the microprocessor is held, other devices are free
to gain access to its memory and I/O space and transfer
data directly using them
• Usually this requires the use of a programmable DMAC
chip: (Direct Memory Access Controller), e.g. the 8237A
• HOLD is sampled during instruction execution while
interrupt signals are sampled at the end of instructions
• HOLD takes effect (HLDA generated) in a clock cycle or two
 So, Hold has a higher priority than interrupts
• The only input with a higher priority than HOLD is the RESET
input to the microprocessor.

DMA finished

Device Requests
I/P DMA Transfer

DMA Request
O/P Granted- mP has relinquished
control of the buses
 DMA Applications
• Wherever large amounts of data need to be transferred
fast between memory and an I/O peripheral device, e.g.
- Hard disk, CD
- Video memory to refresh display
- Sound cards
- Network cards
- Data acquisition boards
• Also for row address generation by hardware to refresh
large DRAMs fast
 I/O
Write
Memory
HOLD Read
C

Simultaneously !
Memory address
Generated by fast
Counters on the DMAC
DMA Control Signals
• Because during a DMA both memory and an I/O device
may be accessed simultaneously, the DMAC may need to
generate:
- #MRDC and #IOWC (simultaneously) for memory to I/O
device transfers
- #IORC and #MRWC (simultaneously) for I/O device to
memory transfers

This was not necessary with programmed I/O as processor

either accessed memory or an I/O device at any given time
moving data between it and the processor
 DMAC Interface

With HLDA
Active

Two types of DMA data transfers: The DMAC is a

Programmable I/O device
1. Sequential DMA: for the microprocessor,
Just like the PPI, PIC,
Read then Write through the DMAC UART, …
Data rests in DMAC. Only M or IO DMA activities by the DMAC
controls are needed at any given time will be programmed into it by
the processor before hand
2. Simultaneous DMA:
Data moved directly between peripheral and memory. Both M & IO controls used at the same time
 The 8237A Programmable DMAC
• Four separate prioritized DMA channels (expandable
by using multiple DMACs)
• Transfer rates up to 1.6 M bytes/s Address bus
(during DMA)
• DMA transfers by the DMA channels are programmed
a priori into the DMAC by
the processor On-chip
Address I/Ps

• Can address 64KB of memory in one mP

 16 I/O adrs
(Programming)

programming operation
 16-bit addresses For address
- Data Bus
(during
Programng)
• Allows the following DMA transfer Counters
- A8-A15
During DMA
DMA
combinations: Device
- Memory to peripheral
- Peripheral to memory
- Peripheral to peripheral
- Memory to memory
• No longer used on the PC in chip form nowadays- its
functionality has been embedded into modern chip
set ICs
Programming the DMAC

(Only these 3 numbers are written into the DMAC)

 DMA Modes: Byte, Burst & Block (3 Bees!)
Bars show
duration
of DMAC
controlling
the buses

Only
for
a
byte

(buffer full)
As long (buffer full)
As Device
Is Ready Block finished?
(filling its buffer)
As long
as needed
to transfer the block
DMAC gets more greedy for bus control

Byte: Burst: (a buffer-full of data) Block: (multiple buffers)

Un-buffered device Fill the buffer of a slow device once Fill the buffer of a fast
Device several times
 Comparison between the three types of I/O
Type Advantages Disadvantages
- Fastest response to device request - Wasted processor
Polling - Simplest hardware and software resources
(always waiting)
- More efficient use of processor time - Delay in response time to
Interrupt- (Processor executes program- interrupt (interrupt latency)
based checks for interrupts only at the end - Overhead due to interrupt
of every instructions) processing, e.g. saving
return address & registers,
context switching
- Increased cost and
complexity of hardware
and software
- Fastest data transfer rates - Need a DMAC device
DMA (approaching those determined by - Highest cost and
memory/device access time) complexity in hardware
Address generation by fast DMAC and software
hardware- not by processor software