AE 773 APPLIED MECHATRONICS

MICROPROCESSOR/
MICROCONTROLLER FUNDAMENTALS

DEPT. OF AEROSPACE ENGINEERING

IIT BOMBAY
 MECHATRONIC SYSTEMS

PRODUCTS, DEVICES, PROCESSES

WHOSE FUNCTIONALITY RELIES ON SYNERGISTIC INTEGRATION OF
MECHANICAL, ELECTRICAL, ELECTRONIC COMPONENTS
CONNECTED BY A CONTROL ARCHITECHTURE

MICROCONTROLLER
(IN MODERN SYSTEMS)
 A microprocessor
• key element of a mechatronic device
• responsible for:
– collecting information
– processing and decision making
– storing
• handle data in digital form
• differences from logic control circuits etc. include:
– programmability
– digital processing
– speed
– ease of integration
– Cost, size..
General Purpose vs Embedded Processors

• General Purpose Processors are mostly used for desk top

computing
• Embedded processors are mostly used for controlling a
system with a fixed function
– designed to consume small amounts of power
– used in everything from
• elevators
• washing machines
• cell phones
• network computers
• set-top boxes for satellite and cable TV
• No of embedded processors >> General purpose
processors
 Microprocessor vs Micro-controllers
• Microprocessors
– high end of market where performance matters
– high power dissipation
– high cost
– need peripheral devices to work
– mostly used in microcomputers
• Microcontollers
– targeted for low end of market where performance does
not matter
– low power dissipation
– low cost
– memory plus I/O de-vices, all integrated into one chip
– Mostly used in embedded systems
 Embedded Systems
• contain microcontroller configured to perform dedicated tasks, along with
any necessary peripheral resources.

• application specific hardware and software.

• software used to control the embedded processor is not accessible to the

user of the device or system.

• required to perform in real time.

• external devices provide a limited user interface to the processor.

• software: ROM – EEPROM, Flash EEPROM; RAM

– On-chip in single chip mode.
– Peripheral devices in expanded mode.

• stand-alone system - processor must run software required to control the

system at power-up.

• embedded systems are often required to be low cost, low power and
small size.
 Outline
• Review Microprocessor Fundamentals
– MPU Register set and Internal Architecture
– MPU buses
– Memory Considerations
– MPU interfacing

• M68HC11 Microcontroller
– Architechture
– Ports and registers
– Application programming
 Review Of MPU Fundamentals
• For Simplicity look at a simple model of
an MPU
– 8-bit
– 64K address space
– Intel style interface
 The CPU
• processes the data by executing a program stored
in the memory
• performs sequence of fetch-and-execute
operations
• consists of:
– Control Unit, ALU, Registers

• responsible for the control of address, data and

control buses (a ‘master’)
• all actions within µP synchronised to the CPU via
a clock signal
• clock signal = a logic square-wave to drive all the
circuitry in the µP, typically 1 to 30 MHz
 The Control Unit
• determines timing and sequence of
operations
• generates timing signals which are used to
fetch program instructions from memory and
to execute it
• also responsible for decoding instructions
• supplies control signals to read and write data
into registers, controls ALU and external
control signals
 The ALU

• The arithmetic and logic unit (ALU) -

responsible for data manipulation
• arithmetic operations, logic operations (AND,
OR, XOR etc.)
• bit shifting, rotating, incrementing,
decrementing, negate, complementing,
addition etc.
 Registers
• Registers – data/adresses that CPU currently
uses - stored in special memory (Small and fast)
locations on the CPU
• accumulator register - input to ALU is stored temp.
• flags register – ALU latest process result
• general purpose register - temporary storage for
data or addresses
• program counter - tracks CPUs position in program
• instruction register -stores instruction where it can
be decoded; not accessible by the programmer
• index registers - hold data address
• stack pointer register - holds the address of the top
of the stack in RAM. Stack - special area of RAM:
last-in first-out (LIFO or FILO) file organisation
• General Registers
• Small set of internal registers - temporary data storage
• CU ensures that data from the correct register is
presented to the CPU
• CU ensures that data is written back to correct register
• Accumulator usually holds ALU result

• Status or Flags Register

OITSZAPC
Overflow Flag
Interrupt Flag
Trap Flag
Sign Flag
Zero Flag
Auxiliary Flag
Parity Flag
Carry Flag
• Stack
• Part of memory where program data can be
stored by a simple PUSH operation
• Restore data by a POP
• Stack is in main memory and is defined by
the program
• Stack Pointer (SP) keeps track of the next
location available on the Stack
• Organised as a FILO Buffer
 Memory Map
Address Bus: 16 bits, 2 16 = 64K locations.
Data Bus: 8 bits (1 byte)

FFFFh

64K possible locations,

each one is 1 byte wide

0000h

1 byte
 µP memory devices
static
RAM
dynamic

MEMORY
PROM
DEVICES

ROM EPROM

EEPROM (E2PROM)
 Buses
• Data bus - to transfer the data associated
with the processing function of the
microprocessor. 8 lines, typically
• Address bus - contains the address of a
specific memory location for accessing stored
data. 16, typically
• Control bus - carries the control signals to
the memory and the I/O devices. Arbitrary
number, often 15
 Buses
• concepts of address and data is fundamental to
the operation of the microprocessor
• memory - consists of locations uniquely
identified by CPU through their address
• CPU communicates with those addresses to
read and write the data - all data.
• the communications go via buses
• the CPU - responsible for control of address,
data and control buses
 Buses
• All devices attached to data bus - potential clash
• Devices connected to data buses can be driven
to high-impedance states
• The ability of devices to set their output at either
logic 1, logic 0 or in a high impedance state is
an essential feature of common bus systems
and is termed a tristate device.
 typical 64k memory map

0xFFFF
0xF000 OS ROM 4K bytes

User RAM 24K bytes

0x9000
0x8000 I/O peripheral 4K bytes

64K byte
Free 24K bytes

0x2000
0x1000 RAM 4K bytes
0x0000 ROM 4K bytes
Memory – physical arrangement
 Memory Read and Write Cycles

• Hardware Control lines used by the CPU to

Control reads and Writes to Memory
• Active low signal RD asserted for a Read
Cycle
• Active Low signal WR indicates a write
• RD and WR signals supply timing information
to memory device
 Read Cycle
Processor puts out RAM
address on the Address
Bus, e.g. 5
0000 0000 0000 0101
(A)
Address
Data
8K bytes D0..D7

Processor reads the

contents of the data bus
CE OE RD

Chip Enable
Output Enable
Read Enable
Processor asserts the
Memory Read signal
 Write Cycle
Processor puts out RAM
address on the Address
Bus, e.g. 9
0000 0000 0000 1001

Address
Data
8K bytes D0..D7

Processor writes the data

to the RAM via the data
CE OE WE bus

Chip Enable
Output Enable
Write Enable
Processor asserts the
Memory Write signal
 Timing diagrams - read/write cycle
1 2

CLOCK CLOCK

ADDRESS address valid ADDRESS address valid

DATA DATA
data valid data valid

READ WRITE

(a) read cycle (b) write cycle

 Read cycle

• It lasts 2 cycles of the clock signal:

1. address of required memory location put on
address bus (by CPU), at rising edge
2. while device held at ‘tristate’ level - control
bus issues ‘read signal’ (active low) to the
device (2nd cycle begins)
3. after delay - valid data placed on data bus
4. levels on the data bus sampled by CPU at
falling edge of the 2nd cycle
 Timing diagrams - read/write cycle
1 2

CLOCK CLOCK

ADDRESS address valid ADDRESS address valid

DATA DATA
data valid data valid

READ WRITE

(a) read cycle (b) write cycle

 Write cycle
1. CPU places address at rising edge
2. decoding logic selects correct device
3. 2nd cycle - rising edge: CPU outputs data onto
data bus & sets WRITE control bus signal active
(LOW)
• Note:
– memory devices & other I/O components have
static logic - do not depend on clock signal-
read data from data bus when write signal high
(inactive) - data must be valid for transition
I/O Instructions vs Memory mapped I/O

• Some processors have separate I/O

instructions with an I/O address space,
separate from memory (Code and Data)
– Allow I/O devices to be decoded separately from
memory devices
• Some processors only support a single
address space - I/O devices are decoded in
the memory map
 Advantages of Memory Mapped I/O

• I/O locations are read/written by normal

instructions - no need for separate I/O
instructions
– Size of instruction set reduced
• Memory manipulations can be performed
directly on I/O locations
• No need for separate IORD and IOWR pins
Advantages of Separate I/O Mapping

• All locations in memory map are available for

memory
– No block removed for I/O
• Smaller, faster instructions can be used for
I/O
• Less Hardware decoding for I/O
• Easier to distinguish I/O accesses in
assembly language
 Interrupts
• Used to Halt the normal flow of instructions
• Exceptions can be due to Hardware or Software
• Hardware Interrupts are asynchronous to the
processor
• Could be asserted by an external device requesting
action, e.g. a port ready to transfer data
• Interrupts can be globally masked by the processor’s
Interrupt Enable Flag (IE or I)
• IE is set by STI and reset by CLI (or equivalent)
Maskable & Non Maskable Interrupts

• Maskable interrupts can be enabled/disabled

using a flag (usually in the flags register
• Non Maskable Interrupts (NMI) are top
priority interrupts that can’t be masked out
• NMIs often used for Parity Errors, Power fails
etc
 Interrupts
Main Program ISR

Interrupt Received
Push Registers
onto the Stack
Complete Current Instruction
PushFlags Register onto Stack
Push Instruction Pointer onto Stack
Clear Interrupt Enable Falg
Trap to Start of ISR BODY of the ISR

Operations shown in
boxes are carried
automatically by MPU
hardware
Pop Registers
from the Stack

Pop flags from the stack

Pop Instruction Pointer from the stack
Resume at restored IP address
Return From Interrupt

Main Program
Resumes
 Instruction sets
• The set of instructions given to the µP to
execute a task is called an instruction set
• Generally, instructions can be classified into the
following categories:
– Data transfer
– Arithmetic
– Logical
– Program control
• Differ depending on the manufacturer, but some
are reasonably common to most µP's.
 Data transfer

• 1. Load
• reads the content of a specified memory location
and copies it to the specified register location in
the CPU
• 2. Store
• copies the current contents of a specified
register into a specified memory location.
 Arithmetic
• 3. Add
• Adds the contents of a specified memory location
to the data in some register
• 4. Decrement
• subtracts 1 from the content of a specified
location.
• 5. Compare
• indicates whether the contents of a register are
greater than, less than or same as the contents of
a specified memory location. The result appears
as a flag in the status register.
 Logical
• 6. AND
• carries out the logical AND operation with the
contents of a specified memory location and the
data in some register
• 7. EXCLUSIVE OR - (similar to 6, but for exclusive OR)
• 8. Logical shift
• moving the pattern of bits in the register one place
to the left or right by moving zero (0) to the end of
the number
• 9. Arithmetic shift
• moving the pattern of bits one place left/right but
with copying of the end number into the vacancy
created by shift
 Program control
• 11. Jump
• changes the sequence in which the program is
executed. So the program counter jumps to some
specified location (other than sequential)
• 12. Branch
• a conditional instruction which might be 'branch if
zero' or 'branch if plus'. It is followed if the right
conditions are met.
• 13. Halt
• stops all further microprocessor activities
 Fetch Decode Execute Cycle
Obtain instruction from program storage
Instruction
Fetch

Instruction Determine required actions and instruction size

Decode

Operand Locate and obtain operand data

Fetch

Execute Compute result value or status

Result Deposit results in storage for later use

Store

Next
Determine successor instruction
Instruction
 Machine Cycles and the System Clock

•Each Machine Cycle is spread across 3 – 4 clock

cycles
•CPU generates additional signals to synchronise
these events with external events (e.g. response
from memory)