Assembly Language

CSSE-402
Chapter 3

Operation of Stored Program

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 A Simple Microcomputer

Data Bus
INPUT
DEVICE Control
Bus
Bus MEMORY
I/O CENTRAL
(RAM AND
PORTS PROCESSING
UNIT (CPU) ROM)
OUTPUT
DEVICE

Address Bus

Major parts: CPU, Memory, I/O

Buses: address bus, data bus, and
control bus.
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Computer Components:
Top Level View
 CPU
❚The central processing unit (CPU) controls the operation
of the computer.
❚Operation of the CPU
❙fetches the instruction from memory
❙decodes the instruction into a series of simple actions
(Performed in the Instruction decoder)
❙executes the instruction by carrying out these actions
in a sequential manner (performed in the logic
control unit)

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 CPU
❚A typical CPU consists of
❙arithmetic-logic unit (ALU) which executes the instructions.
❙logic control unit which interprets and sequences
instructions and generates the bus control signals.
❙special purpose registers such as program counter (PC)
that holds the address of the next instruction or data item
to be fetched from memory.
❙general purpose registers which are used for temporary
storage of binary data- such as accumulator A, status
register, etc.

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 Memor
y
❚Two purposes :
(1)to store the binary codes for the sequences of
instructions that you want the computer to execute
(2)to store the binary-coded data with which the
computer is going to work with.

❚Types:
Usually it consists of a mixture of RAM, ROM and
sometimes bulk storage devices such as floppy disks,
magnetic hard disks or optical disks.

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 Input/Output
❚ Allows the computer to take data from or to the outside world,
through the interface. Peripherals such as keyboards, video
display terminals, printers, and modems are connected to the I/O
sections.
❚ The actual physical devices used to interface the computer buses
to external systems are often called ports.
❚ The simplest type of I/O port is a set of D flip-flops.
❙ If they are being used as an input port, the D inputs are connected to
the external device, and the Q outputs are connected to the data
bus.
❙ Data will then be transferred through the latches when they
are enabled by a control signal from the CPU.
❙ The same concept applies when using the D flip-flop for output.
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 Buses
❚Address bus
❙Unidirectional parallel signal lines connecting CPU and the
memory
❙Bus width; number of lines (wires), can be 16, 20, 24, 32,
or 64 parallel signal lines.
❙On these lines the CPU sends out the address of the
memory location that is to be written to or read from.
❙A CPU with n address lines can address 2n memory
locations. For example, a CPU with 16 address lines can
address 216 or 65,536 (64K) memory locations.

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 Buses
❚Data bus
❙bus width: 4, 8, 16, 32 or 64 bits
❙Bidirectional parallel signal lines (wires)
❙many devices can be connected to the data bus; but only
one at a time can have its output enabled.
❙Any device that is connected to the data bus must have
three-state outputs, so it can be disabled if not being used.

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 Buses
❚Control bus
❙consists of 4 to 10 parallel signal lines.
❙CPU sends out signal on the control bus to enable the
outputs of addressed memory or port devices
❙typical control bus signals: memory read, memory write,
I/O read and I/O write.

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 Buses
❚To read a byte of data from memory location, for
example, consists the following activities:
❙CPU sends out the memory address of the desired byte
on the address bus.
❙CPU sends out a Memory Read signal on the control bus.
❙The Memory Read signal enables the addressed memory
device to output a data word onto the data bus.
❙The data word from the memory travels along the data bus
to the CPU.

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 Hardware, Software, and
Firmware
❚Hardware is the physical devices and circuitry of the
computers.
❚Software is referred to the program written for the
computer.
❚Firmware is the term given to programs stored in
ROMs or in other devices which permanently keep
their stored information.

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 Instruction Cycle

Two steps:
Fetch
Execute
 Fetch Cycle

• Program Counter (PC) holds address of next

instruction to fetch
• Processor fetches instruction from memory
location pointed to by PC
• Increment PC
• Unless told otherwise
• Instruction loaded into Instruction Register (IR)
• Processor interprets instruction and performs
required actions
 Execute Cycle

Processor-memory
data transfer between CPU and main memory
Processor I/O
Data transfer between CPU and I/O module
Data processing
Some arithmetic or logical operation on data
Control
Alteration of sequence of operations
e.g. jump
Combination of above
Example of Program Execution
Instruction Cycle State Diagram
 Interrupts

Mechanism by which other modules (e.g. I/O) may interrupt

normal sequence of processing
Program
e.g. overflow, division by zero
Timer
Generated by internal processor timer
Used in pre-emptive multi-tasking
I/O
from I/O controller
Hardware failure
e.g. memory parity error
Program Flow Control
 Interrupt Cycle

Added to instruction cycle

Processor checks for interrupt
Indicated by an interrupt signal
If no interrupt, fetch next instruction
If interrupt pending:
Suspend execution of current program
Save context
Set PC to start address of interrupt handler
routine
Process interrupt
Restore context and continue interrupted
program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Instruction Cycle (with
Interrupts) - State Diagram
 Multiple Interrupts

Disable interrupts
Processor will ignore further interrupts whilst processing one
interrupt
Interrupts remain pending and are checked after first interrupt has
been processed
Interrupts handled in sequence as they occur
Define priorities
Low priority interrupts can be interrupted by higher priority
interrupts
When higher priority interrupt has been processed, processor
returns to previous interrupt
Multiple Interrupts - Sequential
Multiple Interrupts – Nested
Time Sequence of
Multiple Interrupts
 Connecting

All the units must be connected

Different type of connection for different type of unit
Memory
Input/Output
CPU
Computer Modules
 Memory Connection

Receives and sends data

Receives addresses (of locations)
Receives control signals
Read
Write
Timing
Input/Output Connection(1)

Similar to memory from computer’s viewpoint

Output
Receive data from computer
Send data to peripheral
Input
Receive data from peripheral
Send data to computer
Input/Output Connection(2)

Receive control signals from computer

Send control signals to peripherals
e.g. spin disk
Receive addresses from computer
e.g. port number to identify peripheral
Send interrupt signals (control)
 CPU Connection

Reads instruction and data

Writes out data (after processing)
Sends control signals to other units
Receives (& acts on) interrupts
 Buses

There are a number of possible interconnection

systems
Single and multiple BUS structures are most
common
e.g. Control/Address/Data bus (PC)
e.g. Unibus (DEC-PDP)
 What is a Bus?

A communication pathway connecting two or more

devices
Usually broadcast
Often grouped
A number of channels in one bus
e.g. 32 bit data bus is 32 separate single bit
channels
Power lines may not be shown
 Data Bus

Carries data
Remember that there is no difference between
“data” and “instruction” at this level
Width is a key determinant of performance
8, 16, 32, 64 bit
 Address bus

Identify the source or destination of data

e.g. CPU needs to read an instruction (data) from a
given location in memory
Bus width determines maximum memory capacity of
system
e.g. 8080 has 16 bit address bus giving 64k
address space
 Control Bus

Control and timing information

Memory read/write signal
Interrupt request
Clock signals
Bus Interconnection Scheme
Big and Yellow?

What do buses look like?

Parallel lines on circuit boards
Ribbon cables
Strip connectors on mother boards
e.g. PCI
Sets of wires
Physical Realization of
Bus Architecture
Single Bus Problems

Lots of devices on one bus leads to:

Propagation delays
Long data paths mean that co-ordination of
bus use can adversely affect performance
If aggregate data transfer approaches bus
capacity
Most systems use multiple buses to overcome these
problems
Traditional (ISA)
(with cache)
High Performance Bus
 Bus Types

Dedicated
Separate data & address lines
Multiplexed
Shared lines
Address valid or data valid control line
Advantage - fewer lines
Disadvantages
More complex control
Ultimate performance
 Bus Arbitration

More than one module controlling the bus

e.g. CPU and DMA controller
Only one module may control bus at one time
Arbitration may be centralised or distributed
 Centralised or Distributed Arbitration

Centralised
Single hardware device controlling bus access
Bus Controller
Arbiter
May be part of CPU or separate
Distributed
Each module may claim the bus
Control logic on all modules
 Timing

Co-ordination of events on bus

Synchronous
Events determined by clock signals
Control Bus includes clock line
A single 1-0 is a bus cycle
All devices can read clock line
Usually sync on leading edge
Usually a single cycle for an event
PCI Bus

Peripheral Component Interconnection

Intel released to public domain
32 or 64 bit
50 lines
PCI Bus Lines (required)

Systems lines
Including clock and reset
Address & Data
32 time mux lines for address/data
Interrupt & validate lines
Interface Control
Arbitration
Not shared
Direct connection to PCI bus arbiter
Error lines
 PCI Bus Lines (Optional)

Interrupt lines
Not shared
Cache support
64-bit Bus Extension
Additional 32 lines
Time multiplexed
2 lines to enable devices to agree to use 64-bit transfer
JTAG/Boundary Scan
For testing procedures
 PCI Commands

Transaction between initiator (master) and target

Master claims bus
Determine type of transaction
e.g. I/O read/write
Address phase
One or more data phases
PCI Bus Arbiter
 Execution of a Three-
step Computer
Program
PROGRAM (D. Hall - Figure 2-6 )
Memory 1. Input a value form port 05.
2. Add 7 to this value.
3. Output the result to port 02.
6A 5A 4A 3A 2A 1A 1B 2B 3B 4B 5B 6B 1C 2C3C 4C 5C 6C

CONTROL BUS
SEQUENCE
ADDRESS BUS

DATA BUS

CPU 1A CPU sends out address of first instruction to memory.

1B CPU sends out memory read control signal to enable memory.
CONTROL BUS
1C Instruction byte (E4H) sent from memory to CPU on data bus.
6D 2D
2E 2F 6E 2A Address next memory location to get rest of instruction.
6F
I/O 2B Send memory read control signal to enable memory.
2C Port address byte (05H) sent from memory to CPU on data bus.
2D CPU sends out port address on address bus.
PORT 05 PORT 02
2E CPU sends out port read control signal to enable I/O port.
0 1 2 3 2F Data from port sent to CPU on data bus and store in an
4 5 6 7
8 9 + - internal register.
Display ---------------------------------
Keyboard
(Complete the fetch and execution of 1st instruction)
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 Execution of a Three-
step Computer
Program
3A CPU sends address of next instruction to memory.
3B CPU sends memory read control signal to enable memory.
Memory
3C Instruction byte (04H) from memory sent to CPU on data bus.
4A CPU sends next address to memory to get rest of
6A 5A 4A 3A 2A 1A 1B 2B 3B 4B 5B 6B 1C 2C 3C 4C 5C 6C
instruction.
CONTROL BUS
4B CPU sends memory read control signal to enable memory.
ADDRESS BUS

DATA BUS

CPU 4C Number 07H sent form memory to CPU on data bus.

5A CPU sends address of next instruction to memory.
CONTROL BUS 5B CPU sends memory read control signal to enable memory.
6D 2D
2E 2F 6E 5C Instruction byte (E6H) from memory sent to CPU on data bus.
6F
6A CPU sends out next address to get rest of instruction.
I/O
6B CPU sends out memory read control signal to enable
memory.
PORT 05 PORT 02
6C Port address byte (02) sent from memory to CPU on
0 1 2 3
data bus.
4 5 6 7 6D CPU sends out port address on address bus.
8 9 + -
Display 6E CPU sends out data to port on data bus.
6F CPU sends out output write signal to enable port.
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 Memory Address and Memory
Contents for a three-step Program

MEMORY CONTENTS CONTENTS OPERATION

ADDRESS (BINARY) (HEX)

00100H 11100100 E4 INPUT FROM

00101H 00000101 05 PORT 05H
00102H 00000100 04 ADD
00103H 00000111 07 07H
00104H 11100110 E6 OUTPUT TO
00105H 00000010 02 PORT 02

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 A Typical PC Motherboard
Disk Controller

Video Card

Expansion
Slots

Processor Processor DMA Interrupt Expansion

(8088 up (8087 up controller logic logic
to 80486) to 80487) (8237) (8259)

System
bus
640KB System Timer Keyboard
Dynamic ROM logic logic
RAM (8253) (8255)

Speaker Keyboard
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