Ch1

1.1 BASIC COMPUTER ORGANIZATION:

The address bus is responsible for transmitting the memory address the CPU wants to access. Data is
transferred via the data bus, allowing the CPU to fetch and store data from memory. The control bus
carries control signals that indicate whether data is being read into or written out of the CPU.

the concept of instruction cycles, which are the steps a microprocessor follows to process an instruction.
The microprocessor first fetches the instruction from memory, decodes it to determine the specific
instruction, and then executes the necessary operations.

During the instruction cycle, the microprocessor asserts the READ signal to read data from memory or
I/O devices. The memory subsystem responds by placing the instruction code onto the data bus, which
the microprocessor then reads and stores in its internal register. The READ signal triggers the memory to
read the data, while the WRITE operation causes the memory to store the data.

Timing diagram illustrating the memory read and memory write operations. It explains that the system
clock synchronizes the operations of the microprocessor. In a memory read operation, the
microprocessor places the address on the bus, asserts the READ control signal, reads the data from the
bus, and then removes the address and deasserts the READ signal. The memory write operation follows
a similar sequence but involves asserting the WRITE control signal instead.

The I/O read and write operations are similar to memory read and write operations. It introduces the
concepts of memory-mapped I/O and isolated I/O, where the processor uses a second control signal
(e.g., IO/) to differentiate between I/O and memory accesses.

1.2 CPU ORGANIZATION:

The central processing unit (CPU) is the electronic circuitry responsible for executing instructions in a
computer program. It performs arithmetic, logical, control, and input/output (I/O) operations based on
these instructions.

In a computer system, the major components are interconnected through the system bus. The data bus
facilitates the transfer of data between these components.
To differentiate between memory locations and I/O devices, each element is assigned a unique memory
address. When software wants to access a specific memory location or I/O device, it places the
corresponding address on the address bus. The memory or I/O device with a matching address responds
by reading or writing data on the data bus.

The control bus consists of various signals that govern the communication between the CPU and the rest
of the system. The read and write control lines determine the data flow direction on the data bus. If
both lines are logic one, the CPU and memory/I/O are not communicating. When the read line is low
(logic zero), the CPU reads data from memory, and when the write line is low, data is transferred from
the CPU to memory.

Internally, the CPU is divided into three sections: the register section, the ALU (arithmetic/logic unit),
and the control unit. The register section contains a set of registers, including those specified in the
CPU's instruction set architecture. It interacts with the system address and data buses and also includes
additional registers not directly accessible to the programmer.

During the instruction fetch phase, the CPU outputs the address of the instruction onto the address bus.
The program counter register holds the address of the next instruction to be fetched. The CPU retrieves
this address from the program counter register before outputting it onto the system bus. The instruction
code is read from the system data bus and stored in the instruction register.

The ALU performs arithmetic and logic operations, receiving operands from the register section and
storing the results back in the registers.

The control unit, which receives data values from the register unit, generates control signals. It
generates instruction codes, sets values in flag registers, and produces signals for the system control
bus, such as READ, WRITE, and IO/

1.2 MEMORY SUBSYSTEM ORGANIZATION AND INTERFACING:

Memory Subsystem Organization:

Memory is composed of circuits used to store data, with each memory chip having a fixed number of
memory locations, and each location storing a binary value of a fixed length. The size of a memory chip
is determined by the number of locations multiplied by the number of bits in each location.

The memory unit is viewed as a black box, and data transfer between the memory and the processor
occurs through two registers: The Memory Address Register (MAR) and the Memory Data Register
(MDR). The MAR holds the address being accessed, while the MDR holds the data being transferred
between the memory and the processor.

Internal Organization of Memory Chips:

Memory is often organized in arrays, with each cell capable of storing one bit of information. Cells are
arranged in rows and columns, with each row forming a memory word. The cells in each column are
connected to sense/write circuits through two bit lines. The sense/write circuits are responsible for
reading and writing data to and from the cells.

Types of Memory Chips:

Read-Only Memory (ROM): ROM chips are programmed with data before being added to the computer
system. They retain their data even when power is turned off. There are different types of ROM,
including masked ROM, PROM (Programmed Read-Only Memory), EPROM (Electrically Programmable
Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), and Flash
Memory.

Random Access Memory (RAM): RAM chips are volatile memory that allows both reading and writing of
data. They do not retain data when power is removed. RAM chips can be further categorized into
Dynamic RAM (DRAM) and Static RAM (SRAM). DRAM chips need to be periodically refreshed, while
SRAM chips do not require refreshing.

Memory Subsystem Configuration:

Multiple memory chips can be combined to create memory with more bits per location. This is achieved
by connecting the address and control signals of the chips and connecting their data pins to different
bits of the data bus. Interleaving techniques, such as higher-order interleaving and lower-order
interleaving, are used to select the appropriate chip based on address patterns.

Multi-Byte Organization:

In some data formats, more than one 8-bit byte is used to represent a value. The order in which these
bytes are stored in memory can follow either big-endian or little-endian systems. In big-endian systems,
the most significant byte has the lowest address, while the least significant byte has the highest address.
In little-endian systems, the least significant byte has the lowest address, while the most significant byte
has the highest address.
1.3 I/O SUBSYSTEM ORGANIZATION AND INTERFACING:
The I/O Subsystem:

The I/O subsystem is treated as an independent unit in the computer system. The CPU initiates I/O
commands generically, such as read, write, or scan, simplifying the CPU's tasks.

Input Device Interface:

The generic interface circuitry for an input device, such as a keyboard, is shown. The data from the input
device is passed through tri-state buffers. When the address and control signals are correct, the buffers
are enabled, and the data passes onto the data bus. The CPU can then read this data. If the conditions
are not met, the buffers remain disabled, and the data is not placed on the bus.

Output Device Interface:

The design of the interface circuitry for an output device, such as a computer monitor, differs from that
of an input device. Tri-state buffers are replaced by a register. Since output devices read from the bus
instead of writing data to it, the tri-state buffers are not necessary. When the load logic receives the
correct address and control signals, it asserts the data bus. The output device can read the data from the
register at its leisure while the CPU performs other tasks.

Bidirectional I/O Devices:

Some devices are used for both input and output, such as personal computers and hard disk devices.
These devices require a combined interface that essentially consists of two interfaces—one for input
and one for output.

1.4 LEVELS OF PROGRAMMING LANGUAGES

Levels of Programming Languages:

Computer programming languages are divided into three categories:

High-Level Languages:

High-level languages are platform-independent, meaning that programs written in these languages can
run on computers with different microprocessors and operating systems without modifications.
Examples of high-level languages include C++, Java, and FORTRAN. High-level languages provide a higher
level of abstraction and are easier to read and write compared to lower-level languages.
Assembly-Level Language:

Assembly languages are at a lower level of abstraction. Each microprocessor has its own assembly
language, and a program written in the assembly language of one processor cannot be run on a
computer with a different processor. Assembly languages are platform-dependent. Instructions in
assembly languages directly manipulate the data stored in the microprocessor's internal components.
Assembly language instructions can load data from memory into microprocessor registers, perform
arithmetic and logical operations, and control the flow of execution.

Machine-Level Language:

Machine-level languages are the lowest level of programming languages. These languages contain
binary values that directly control the microprocessor's operations. When a microprocessor reads and
executes an instruction, it is operating at the machine level. Machine-level languages are specific to a
particular microprocessor architecture and are not human-readable. They consist of binary patterns
representing instructions and data.

Program Translation Process:

Programmers typically do not write programs directly in machine language. Instead, programs are
written in assembly or high-level languages and then converted into machine code for execution by the
microprocessor. The process of converting a program from a high-level language or assembly language
to machine language involves several steps:

High-Level Language Compilation:

For programs written in high-level languages, a compiler is used. The compiler checks the syntax and
semantics of the program, generates an object code file, and performs optimizations. The object code is
the machine language equivalent of the source code.

Assembly Language Assembly:

For programs written in assembly language, an assembler is used. The assembler translates the
assembly language instructions into machine code instructions and generates an object code file.

Linking and Executable File Creation:

The object code generated from the compilation or assembly process is combined with other object
code files, libraries, or system components using a linker. The linker resolves references between
different parts of the program and creates an executable file that can be directly executed by the
operating system.
1.5 ASSEMBLY LANGUAGE INSTRUCTIONS:
Assembly Language Instructions:

simple computer organization with one processor register and instruction code format consisting of two
parts: the operation code and the address. The memory address specifies where to find an operand in
memory, which is then operated on along with the data stored in the processor register.

Instruction Formats:

The basic computer discussed in the section has three instruction code formats, each consisting of 16
bits:

Memory Reference Instruction:

This instruction uses 12 bits to specify an address and one bit to indicate the addressing mode (direct or
indirect).

Register-Reference Instruction:

These instructions are recognized by the operation code 111 with a 0 in the leftmost bit (bit 15) of the
instruction. They specify operations or tests on the accumulator (AC) register.

Input-Output Instruction:

These instructions are recognized by the operation code 111 with a 1 in the leftmost bit of the
instruction. They specify input-output operations or tests.

Instruction Types:

Assembly language instructions are grouped into three main types based on their operations:

Data Transfer Instructions: These instructions involve loading, storing, moving, inputting, or outputting
data between memory and the microprocessor.

Data Operational Instructions: These instructions perform operations on data, including arithmetic
operations, logical operations, and shift operations.
Program Control Instructions: These instructions control the flow of a program, including jump or branch
instructions, interrupt instructions, and halt instructions.

1.6 Instruction set architecture(ISA) design:

Designing an Instruction Set Architecture (ISA) is a crucial aspect of microprocessor design. A well-
designed ISA can result in a powerful and versatile processor, while a poorly designed one can lead to
limitations and inefficiencies. When designing an ISA, several factors need to be considered, including
performance, size, cost, completeness, instruction orthogonality, and register set.

For general-purpose computing, such as personal computers, a rich and comprehensive ISA is typically
required to accommodate a wide range of tasks. This usually involves a large instruction set and a
significant number of registers to handle various types of programs effectively. For specialized
applications like a microwave oven, a simpler and more targeted ISA may be sufficient, avoiding
unnecessary hardware complexity.

Here is an overview of a relatively simple ISA design for a microprocessor:

Memory:

The microprocessor can access 64K (216) bytes of memory, with each byte consisting of 8 bits.

The system using this processor can have less memory if the full 64K is not required.

Input/output (I/O):

Two types of I/O interactions can be designed: isolated I/O and memory-mapped I/O.

In isolated I/O, separate instructions are used for memory and I/O operations.

In memory-mapped I/O, I/O devices are treated as memory locations, accessed using the same
instructions as memory.

Registers:

Accumulator (AC): An 8-bit register that receives the result of arithmetic and logical operations. It can be
used as an operand for ALU instructions.

Register R: An 8-bit general-purpose register that serves as the second operand for two-operand
arithmetic and logical instructions and stores the final data.
Zero flag (Z): A 1-bit flag that is set to 1 if the result of an arithmetic or logical instruction is zero, and 0
otherwise.

Instruction Set Architecture:

The ISA includes data transfer instructions, program control instructions, and data operational
instructions.

Data transfer instructions: NOP (no operation), LDAC (load AC from memory), STAC (store AC to
memory), MOVAC (move data from R to AC), and MOVR (move data from AC to R).

Program control instructions: JUMP (unconditional jump to a memory location), JUPZ (jump if zero flag is
0), and JPNZ (jump if zero flag is 1).

Data operational instructions: ADD (add AC and R), SUB (subtract R from AC), INAC (increment AC by 1),
CLAC (clear AC to 0), AND (logical AND of AC and R), OR (logical OR of AC and R), XOR (logical XOR of AC
and R), and NOT (bitwise complement of AC).

1.7 RELATIVELY SIMPLE COMPUTER:

In this relatively simple computer, all the hardware components are integrated into one system. The
computer consists of an 8K ROM (Read-Only Memory) starting at address 0, followed by an 8K RAM
(Random Access Memory). Additionally, there is a memory-mapped bidirectional I/O port located at
address 8000H.

Let's examine the CPU, which utilizes a 16-bit address bus labeled A15 through A0 and a system bus
through pins D7 to D0. The CPU also includes two control lines: READ and WRITE.

To access a memory chip, the processor needs to provide an address that the chip can interpret. An 8K
memory chip has 2^13 (or 213) internal memory locations, requiring 13 address bits to select one of
these locations. Each memory chip receives the CPU's address bits A12 to A0 from the system address
bus. The remaining three bits, A15, A14, and A13, are used to select one of the memory chips.

The address range of the ROM and RAM is as follows:

ROM: Addresses 0000H to 1FFFH (8K address space)

RAM: Addresses 2000H to 3FFFH (8K address space)

UNIT- II
ORGANIZATION OF A COMPUTER

2.1 Register Transfer Language:

A digital system is composed of interconnected digital hardware modules, which can range in size and
complexity from a few integrated circuits to a complex network of interacting digital computers. The
design of digital systems typically follows a modular approach, where modules are constructed using
digital components such as registers, decoders, arithmetic elements, and control logic. These modules
are connected through data and control paths to form a digital computer system.

Digital modules are characterized by the registers they contain and the operations performed on the
data stored in those registers. These operations are referred to as micro operations, which are
elementary operations executed on the information stored in one or more registers. Examples of micro
operations include shifting, counting, clearing, and loading.

The internal organization of a digital computer system can be defined by specifying:

The set of registers it contains and their functions.

The sequence of micro operations performed on the binary information stored in the registers.

The control mechanism that initiates the sequence of micro operations.

To describe the transfers of micro operations among registers, a symbolic notation called a register
transfer language is used. The term "register transfer" implies the presence of hardware logic circuits
capable of performing specific micro operations and transferring the results to the same or different
registers.

The concept of "language" is borrowed from programming languages, as programmers use languages to
specify computational processes. Similarly, a register transfer language provides a symbolic system for
expressing micro operation sequences among the registers in a digital module. It serves as a concise and
precise tool for describing the internal organization of digital computers and can aid in the design
process of digital systems.
The chosen register transfer language aims to be as simple as possible, allowing for quick memorization.
It defines symbols for various types of micro operations and describes the associated hardware needed
to implement these micro operations. While there may be variations in register transfer languages, with
different symbol sets, the overall purpose remains the same, and familiarity with one language can ease
the learning process of others.

By using a register transfer language, the design and operation of digital systems can be effectively
communicated and understood in a standardized and systematic manner.

2.2 Register Transfer:

Computer registers are identified by capital letters, sometimes followed by numerals, to indicate their
function. For example, MAR, PC, IR are register names. Registers can be represented in block
diagram form, as shown in Figure 1. The most common representation of a register is a rectangular
box with the register name inside (Figure 1a). The individual bits within a register can also be
distinguished (Figure 1b). In a 16-bit register, the numbering of bits can be marked on top of the box
(Figure 1c). A 16-bit register can be partitioned into two parts, such as a low byte (bits 0-7) and a
high byte (bits 8-15) (Figure 1d). The name of the 16-bit register in this example is PC, with PC (0-7)
or PC(L) referring to the low-order byte and PC (8-15) or PC(H) to the high-order byte.

Information transfer from one register to another is represented symbolically using a replacement
operator. The statement "R2 <-- R1" denotes a transfer of the content of register R1 into register R2.
This implies replacing the content of R2 with the content of R1, while the content of R1 remains
unchanged.

A register transfer statement assumes the availability of circuits connecting the outputs of the source
register to the inputs of the destination register, and the destination register should have a parallel
load capability. The transfer operation usually occurs only under a predetermined control condition,
which can be expressed using an if-then statement. For example: "If (P = 1) then (R2 <-- R1)" states
that the transfer should happen only when the control signal P is equal to 1. Control variables can be
separated from the register transfer operation by specifying a control function, which is a Boolean
variable that can take the values 1 or 0. The control function is included in the statement as follows:
"P: R2 <-- R1."

Every statement in the register transfer notation implies a hardware implementation for the transfer
operation. The block diagram in the figure illustrates the transfer from register R1 to R2, where the n
outputs of R1 are connected to the n inputs of R2.
The basic symbols used in register transfer notation are listed in Table 1. Registers are denoted by
capital letters, and numerals may follow the letters. Parentheses () are used to denote a part of a
register, arrows denote the transfer of information, and commas (,) separate two micro operations.
For example, "T: R2 R1, R1 R2" denotes an operation that exchanges the contents of two registers
(R1 and R2) during one common clock pulse, provided that T = 1. This simultaneous operation is
possible with registers that have edge-triggered flip-flops.

2.3 Bus and Memory Transfers:

A typical digital computer consists of multiple registers, and transferring information between these
registers can result in excessive wiring if separate lines are used between each register. To address
this issue, a more efficient scheme is to use a common bus system.

A bus structure is composed of a set of common lines, with each line representing a bit of a register.
Binary information is transferred one bit at a time through these lines. Control signals determine
which register is selected by the bus during each register transfer.

In the diagram shown, the bits in the same significant position in each register are connected to the
data inputs of one multiplexer, forming one line of the bus. Each multiplexer, such as MUX 0, MUX
1, etc., multiplexes the corresponding bits of the registers.

Two selection lines, S1 and S0, are connected to the selection inputs of all four multiplexers. The
selection lines determine which bits of a register are chosen and transferred into the common bus. For
example, when S1S0 = 00, the 0 data inputs of all four multiplexers are selected, causing the bus
lines to receive the content of register A. The table provided shows the register selected by the bus
for each possible binary combination of the selection lines.

In general, a bus system can multiplex k registers of n bits each to produce an n-line common bus.
The number of multiplexers needed is equal to the number of bits in each register (n), and each
multiplexer must have k data input lines and the necessary selection lines.

To transfer information from a bus to a destination register, the bus lines are connected to the inputs
of all destination registers. The load control input of the selected destination register is then activated
to load the content of the bus into the register.

Symbolically, a bus transfer can be represented as "BUS C, R1 BUS," where the content of register C
is placed on the bus, and the content of the bus is loaded into register R1 by activating its load control
input. Alternatively, if the presence of the bus is known, a direct transfer can be shown as "R1 C,"
indicating that the content of the bus is transferred to register R1.

Instead of using multiplexers, a bus system can be constructed using three-state gates. Three-state
gates exhibit three states: logic 1, logic 0, and a high-impedance state. Three-state buffer gates are
commonly used for constructing a bus system. These gates have both a normal input and a control
input that determines the output state.

The construction of a bus system using three-state buffers involves using n circuits, each with four
buffers, to multiplex one significant bit from each register. Each group of four buffers corresponds to
one line in the common bus, and a decoder is used to select between the registers.

Memory transfer operations involve reading from and writing to memory. The memory word is
represented by the letter M and is selected by the memory address during the transfer. The read
operation transfers information from the selected memory word to a data register (DR) specified by
the read operation statement, such as "Read: DR [AR]," where AR is the address register.

The write operation transfers the content of a data register (e.g., R1) to the memory word selected by
the address. The write operation statement typically specifies the memory address in square brackets
following the letter M, such as "M[AR] R1."

The micro operations listed in Table 3 include the basic arithmetic and logical operations that can be
performed on registers. The micro operations for increment and decrement are represented by plus
one and minus one operations, respectively. These micro operations can be implemented using
combinational circuits or binary up-down counters.

It should be noted that the micro operations of multiplication and division, while valid arithmetic
operations, are not included in the basic set of micro operations. They are typically implemented
using specialized circuits in a digital system and are not considered as micro operations in the
traditional sense.

2.4 Arithmetic micro operations:

Binary Adder: A binary adder is a digital circuit used to perform arithmetic addition of two binary
numbers. It consists of full-adder circuits connected in cascade, with the carry output of one full-
adder connected to the carry input of the next.
Binary Adder-Subtractor: The subtraction of binary numbers can be accomplished by taking the 2's
complement of the subtrahend and adding it to the minuend. By including an exclusive-OR gate with
each full-adder, an adder-subtractor circuit can be created to perform both addition and subtraction
operations.

Binary Incrementer: The increment micro operation adds one to a number in a register. It can be
implemented using a binary counter or a combinational circuit independent of a specific register.

Arithmetic Circuit: An arithmetic circuit combines the basic arithmetic microoperations (such as
addition, subtraction, increment) into a composite circuit. It utilizes a parallel adder and control
inputs to generate different arithmetic operations.

Logic Micro operations: Logic micro operations manipulate individual bits or bit strings stored in
registers. They treat each bit separately as binary variables and can perform operations like AND,
OR, XOR, and complement.

Hardware Implementation: Logic micro operations are implemented using logic gates that perform
the required logic function on each bit or pair of bits in the registers.

Applications: Logic micro operations are useful for manipulating bits or portions of words in
registers. They can be used for bit manipulation, bit value changes, deletion or insertion of bits, and
logical decision-making.

Selective-Set: Sets the bits in a register to 1 where there are corresponding 1's in another register.

Selective-Complement: Complements the bits in a register where there are corresponding 1's in
another register.

Selective-Clear: Clears the bits in a register to 0 where there are corresponding 1's in another register.

Mask Operation: Clears specific bits in a register based on the corresponding bits in another register,
typically achieved using an AND operation. (0 -> 0), (1-> A)
Insert Operation: Inserts a new value into a group of bits in a register, typically achieved using an OR
operation after masking the unwanted bits. (0-> A)

Clear Operation: Compares two registers and produces an all-0 result if they are equal, typically
achieved using an exclusive-OR operation.

These micro operations provide essential building blocks for performing arithmetic and logic
operations in digital systems and are utilized in various computational tasks and data manipulation
operations.

2.5 Shift Micro operations:

The given excerpt describes shift micro operations in computer architecture. Shift micro operations
are used for serial transfer of data and are often used in conjunction with arithmetic, logic, and other
data-processing operations.

There are three types of shifts: logical shift, circular shift, and arithmetic shift.

Logical Shift: In a logical shift, 0 is transferred through the serial input. It can be further classified
into logical shift-left (shl) and logical shift-right (shr). During a shift-left operation, the serial input
transfers a bit into the rightmost position, while during a shift-right operation, the serial input
transfers a bit into the leftmost position.
Example:

R1 shl R1: Specifies a 1-bit shift to the left of the content of register R1.
R2 shr R2: Specifies a 1-bit shift to the right of the content of register R2.
Circular Shift: A circular shift also transfers 0 through the serial input. However, in a circular shift,
the shifted bit is transferred back to the other end of the register, creating a circular pattern. Circular
shifts are denoted as csl (circular shift-left) and csr (circular shift-right).

Arithmetic Shift: An arithmetic shift is used for shifting signed binary numbers to the left or right. In
an arithmetic shift-left, the signed binary number is multiplied by 2, while in an arithmetic shift-right,
the number is divided by 2. Arithmetic shifts must preserve the sign bit, as the sign of the number
remains the same when multiplied or divided by 2. The leftmost bit in a register holds the sign bit,
and the remaining bits hold the number.
It is important to handle overflow in arithmetic shifts. If V, (overflow) is 0, there is no overflow.
However, if V, is 1, there is an overflow and a sign reversal after the shift. The overflow value (V,)
needs to be transferred into the overflow flip-flop with the same clock pulse that shifts the register.

For hardware implementation, a bidirectional shift register with parallel load can be used.
Alternatively, a combinational circuit can be implemented, which is more efficient in systems with
multiple registers. The combinational circuit shifter can be constructed using multiplexers. The data
to be shifted is placed onto a common bus, which is then connected to the combinational shifter. The
shifted value is loaded back into the register with a single clock pulse.

The provided excerpt also mentions a 4-bit shifter as an example, where multiplexers are used to
implement the shifting operations. The shifter has four data inputs (A0 through A3) and four data
outputs (H0 through H3). It includes two serial inputs for shift left (IL) and shift right (IR). The
selection input (S) determines the shift direction. The function table determines the output for each
input after the shift. The number of multiplexers required in a shifter depends on the number of data
inputs and outputs. The serial inputs can be controlled by another multiplexer to provide the three
possible types of shifts.

2.6 Arithmetic Logic Shift Unit:

Arithmetic Logic Shift Unit (ALU) that combines arithmetic, logic, and shift circuits into a single
unit. The excerpt mentions that one stage of the ALU is shown in Figure 13.

Figure 13 represents the ALU stage and provides a total of 14 operations, including 8 arithmetic
operations, 4 logic operations, and 2 shift operations. These operations are selected using five
variables: 53, 52, 51, 50, and C. The input carry C. is used exclusively for selecting arithmetic
operations.

Table 8 provides a list of the 14 operations supported by the ALU. The first eight operations are
arithmetic operations, and they are selected when 5352 = 00. The next four operations are logic
operations and are selected when 5352 = 01.
2.7 Control memory:
Control memory is typically implemented using a read-only memory (ROM). The content of ROM
words is fixed and cannot be altered easily.

Microinstructions, which contain control variables and specify micro operations for the control unit,
are stored in the ROM. The control unit accesses these microinstructions through read operations.
Dynamic microprogramming allows for more flexibility by initially loading the microprogram from
an auxiliary memory, such as a magnetic disk. This approach uses a writable control memory that
allows for changes to the microprogram.

The control memory is a part of the control unit and holds the microinstructions. It is often assumed
to be a ROM.

In the general configuration of a microprogrammed control unit shown in Figure 14, the control
memory address register specifies the address of the microinstruction, and the control data register
holds the microinstruction read from memory.

Each microinstruction contains a control word that specifies one or more micro operations to be
executed by the data processor. After executing these operations, the control unit determines the next
address.

The microprogram residing in the control memory can be changed to accommodate different
operations, without requiring changes to the hardware configuration.

Figure 14 demonstrates the block diagram of a microprogrammed control organization, showing the
components involved, including the control memory, control memory address register, control data
register, and the relationship between the control unit and the data processor.

2.8 Address Sequencing:

Microinstructions are grouped and stored in control memory, with each group representing a routine
for executing a specific computer instruction.

The control unit's hardware is responsible for sequencing the microinstructions within a routine and
enabling branching between different routines.

During the execution of a computer instruction, the control unit undergoes several steps. An initial
address is loaded into the control address register, usually pointing to the first microinstruction of the
instruction fetch routine.

The fetch routine fetches the instruction from memory and stores it in the instruction register.

The control unit generates micro operations based on the instruction's operation code, which
determines the microprogram routine stored in a specific location in control memory. This mapping
process converts the instruction code bits into a control memory address.

Once the appropriate routine is reached, the microinstructions for executing the instruction are
sequenced, potentially based on the values of certain status bits in processor registers.

Microprograms that use subroutines require an external register for storing the return address, as
return addresses cannot be stored in the control memory.

After the instruction execution is completed, control typically returns to the fetch routine by
executing an unconditional branch microinstruction to its first address.
Address sequencing capabilities required in a control memory include incrementing the control
address register, unconditional and conditional branching based on status bit conditions, mapping the
instruction bits to control memory addresses, and supporting subroutine calls and returns.

Figure 7-2 illustrates a block diagram of control memory and the associated hardware for selecting
the next microinstruction address. Conditional branching is enabled through status conditions in the
system that provide parameter information.

The mapping of instructions involves transforming the operation code bits of an instruction into a
control memory address. A simple mapping process example is provided, where the operation code is
used to determine the address in control memory corresponding to the microprogram routine for that
instruction.

Subroutines are used to reuse common sections of microcode, saving microinstructions. They require
storing the return address during a subroutine call and restoring it during a subroutine return.

2.8 Design of Control Unit:

Microinstructions are typically divided into fields, where each field represents a distinct function.
These fields contain control bits that initiate micro operations, specify the address evaluation method,
and provide branching addresses.

Grouping mutually exclusive variables into fields and encoding them using k bits can reduce the
number of control bits required to initiate micro operations. Each field is decoded using a decoder to
generate the corresponding control signals.

This encoding and decoding method reduces the size of the microinstruction bits but requires
additional hardware outside the control memory. It also introduces delay as the control signals need
to propagate through the decoding circuits.

The excerpt mentions the use of three decoders in the control unit. Each field of the microinstruction
is decoded using a 3 x 8 decoder, resulting in eight outputs for each field.

The outputs of the decoders are connected to various components of the system based on their
functionality. For example, the outputs of decoder f1 are connected to the load input of the address
register (AR), allowing information from multiplexers to be transferred to AR based on the active
decoder outputs.

Multiplexers are used to select information from different sources, such as the data register (DR) or
program counter (PC), based on the active decoder outputs.

Similar connections need to be made from the decoder outputs associated with arithmetic and logic
operations to the arithmetic logic shift unit (ALU) or relevant components.

The design of the control unit involves organizing the microinstructions into fields, encoding these
fields, and using decoders to generate control signals for initiating micro operations. The decoded
outputs are then connected to the appropriate components of the system to execute the desired
operations.
2.10 Microprogram Sequencer:
A microprogram sequencer can be constructed using digital functions tailored to a specific
application. However, general-purpose sequencers available as integrated circuits can be used for the
construction of microprogram control units.

An integrated circuit microprogram sequencer should have an internal organization that can be
adapted to a wide range of applications to ensure its versatility.

The block diagram of the microprogram sequencer includes the control memory, which interacts with
the sequencer.

The microprogram sequencer consists of two multiplexers. The first multiplexer selects an address
from four different sources and routes it to the control address register (CAR).

The second multiplexer compares the value of a selected status bit with a test value. The result of this
comparison is fed into an input logic circuit.

The output from the control address register (CAR) serves as the address for the control memory.
The content of CAR is incremented and is also applied to the subroutine register (SBR).

The input logic circuit in the microprogram sequencer has three inputs (l0, l1, and T) and three
outputs (S0, S1, and L). The selection variables (So and S1) determine the path in the multiplexer,
selecting one of the four inputs for the control address register (CAR).

Each input and output of the multiplexer contains a 7-bit address.

The microprogram sequencer is responsible for selecting the appropriate addresses for the control
memory, incrementing the control address register, and handling subroutine calls by transferring
addresses between the subroutine register and the control address register. The sequencer uses
multiplexers and input logic circuits to control the sequencing of microinstructions based on the
selected status bit and test values.

Chapter 4
the design and implementation of combinational logic circuits in embedded systems. The main topics
covered include designing combinational logic circuits for various scenarios, such as adders, subtractors,
comparators, multiplexers, demultiplexers, encoders, decoders, and code converters. The chapter also
introduces design methods and considerations for practical circuit implementation.

The design of combinational logic circuits begins with stating the problem and specifying the number of
inputs and outputs. Truth tables are constructed to define the relationship between inputs and outputs,
and Boolean functions are derived using methods like K-Maps, tabulation, and Boolean algebra rules.
The simplified Boolean functions are then used to create logic diagrams.
The chapter explores specific applications of combinational logic circuits, including adders for
performing arithmetic operations, subtractors for subtraction operations, comparators for comparing
two numbers, multiplexers for selecting input lines, demultiplexers for distributing input to multiple
output lines, encoders for converting information from one format to another, and decoders for
converting binary information to output lines.

Code converters are also discussed, such as converting binary to Gray code, and their advantages over
binary numbers are highlighted.

Finally, the chapter mentions the implementation of these circuits using circuit board design and
simulation software like Electronics Workbench (EWB) or Multisim.