Assembly Language

CSSE-402

Chapter 1 Overview

1
 Books

Books:
1.Microprocessor and interfacing
By Daglus V. Hall (3rd ed)

2.8088/8086, 80286 ,80386…………….core

BY barry B. Bray (8th ed)
 Computer Generations

Approximate Typical Speed

Generation Dates Technology (operations per second)

1 1946-1957 Vacuum tube 40,000

2 1958-1964 Transistor 200,000

3 1965-1971 Small and medium 1,000,000

scale integration
4 1972-1977 Large scale 10,000,000

integration
5 1978-1991 Very large scale 100,000,000

integration Over 100,000,000

6 1991- Ultra large scale
integration
 Growth in Chip Density
1011
GSI
10
Components per Chip

10
109
ULSI
108

107
VLSI
106

105
LSI
104
103 MSI

102
SSI
101
100
1960 1970 1990 2000 2010 2020
1980 ZSI
ZSI = Zero-Scale Integration (Discrete Components) VLSI = Very-Large-Scale Integration
SSI = Small-Scale Integration ULSI = Ultra-Large-Scale Integration
MSI = Medium-Scale Integration GSI = Giga-Scale-Integration
LSI = Large-Scale Integration
Evolution of DRAM and Processor
Characteristics
Morre’s Law: The number of transistors doubles every 18-24 months.

200 Dynamic RAM Density

100
Improvement factor

50
Processor Speed
20

10

5
Dynamic RAM Speed

1
1980 1985 1990 1995
 Trends in DRAM Use
256
Supercomputers
128 8Gbytes
Servers

64 2Gbytes
Number of DRAMS

32 Workstations 512Mbytes

16
128Mbytes

8 Large PCs 32Mbytes

4 8Mbytes
Small PCs
2Mbytes
2

1
1986 1987 1988 1989 1990 1991 1996 1997 1998 1999 1999
1992 1993 1994 1995

DRAM Size 1Mbits 4Mbits 16Mbits 64Mbits 256Mbits

Predominant 1M1 1M4 4M4 ??? ???
256K 2M8
Organization 4
 Moore’s Law
• Increased density of components on chip
• Gordon Moore – co-founder of Intel
• Number of transistors on a chip will double every year
• Since 1970’s development has slowed a little
• Number of transistors doubles every 18 months
• Cost of a chip has remained almost unchanged
• Higher packing density means shorter electrical paths, giving higher
performance
• Smaller size gives increased flexibility
• Reduced power and cooling requirements
• Fewer interconnections increases reliability
 Evolution of Intel
Microprocessors
Feature 8088 8080 8086 80396 80486 P entium P6 P -II Celeron PII Xeon

Year introduced 1972 1974 1978 1985 1989 1993 1995 1997 1998 1998

Num ber of instructions 66 111 133 154 235

Address bus width 8 16 20 32 32 32 64 64 32 64

Data bus width 8 8 16 32 32 64 64 64 64 64

Num ber of flags 4 5 9 14 14

Num ber of registers 8 8 16 8 8

Mem ory addressability 16 KB 64 KB 1MB 4GB 4G B 4G 64G 64G 4G 64G

I/O ports 24 256 64 K 64 K 64K

Bus bandwidth (M B/sec) - 0.75 5 32 32

Register-to-register - 1.3 0.3 0.125 0.06

add tim e (sec)
x86 Evolution (1)
8080
first general purpose microprocessor
8 bit data path
Used in first personal computer – Altair
8086 – 5MHz – 29,000 transistors
much more powerful
16 bit
instruction cache, prefetch few instructions
8088 (8 bit external bus) used in first IBM PC
80286
16 Mbyte memory addressable
up from 1Mb
80386
32 bit
Support for multitasking
80486
sophisticated powerful cache and instruction pipelining
built in maths co-processor
 x86 Evolution (2)

Pentium
Superscalar
Multiple instructions executed in parallel
Pentium Pro
Increased superscalar organization
Aggressive register renaming
branch prediction
data flow analysis
speculative execution
Pentium II
MMX technology
graphics, video & audio processing
Pentium III
Additional floating point instructions for 3D graphics
x86 Evolution (3)
Pentium 4
Note Arabic rather than Roman numerals
Further floating point and multimedia enhancements
Core
First x86 with dual core
Core 2
64 bit architecture
Core 2 Quad – 3GHz – 820 million transistors
Four processors on chip

x86 architecture dominant outside embedded systems

Organization and technology changed dramatically
Instruction set architecture evolved with backwards compatibility
~1 instruction per month added
500 instructions available
See Intel web pages for detailed information on processors
8086 Pin
Diagram
GND 1 Vcc
AD14 40 AD15
2 A16/S3
AD13 39
3 A17/S4
38
AD12
4
A18/S5
37
AD11
5
36 A19/S6
AD10 6 BHS /S7
AD9 35 MN/MX
AD8 7 RD
AD7 34 RQ
S2 / GT0 (HOLD)
( M/IO)
AD6 8 RQ /
S1 ( GT1 (HLDA)
AD5 33 DT/R) ( WR )
LOCK
AD4 9 S0 ((ALE)
DEN)
QS0
32
AD3 QS1 (INTA)
AD2 10 8086 31 TEST
AD1 11 CPU READY
AD0 30
NMI 12 RESET
INTR 29 40 LEAD
CLK 13
28
GND
14
27
15
26
16
Block Diagram of a Simple
8086- based
Microcomputer
8086 Architecture
8086 Architecture
80286 Architecture
80386 Architecture
Intel 486 Internal Block
Diagram
Pentium Architecture
Pentium-III Architecture
Pentium-IV Architecture
Core Architecture
Core i7 Architecture
 Embedded Systems
ARM

ARM evolved from RISC design

Used mainly in embedded systems
Used within product
Not general purpose computer
Dedicated function
E.g. Anti-lock brakes in car
Embedded Systems
Requirements
Different sizes
Different constraints, optimization, reuse
Different requirements
Safety, reliability, real-time, flexibility, legislation
Lifespan
Environmental conditions
Static v dynamic loads
Slow to fast speeds
Computation v I/O intensive
Descrete event v continuous dynamics
Possible Organization of an Embedded
System
 ARM Evolution
Designed by ARM Inc., Cambridge, England
Licensed to manufacturers
High speed, small die, low power consumption
PDAs, hand held games, phones
E.g. iPod, iPhone
Acorn produced ARM1 & ARM2 in 1985 and ARM3 in 1989
Acorn, VLSI and Apple Computer founded ARM Ltd.
 ARM Systems Categories

Embedded real time

Application platform
Linux, Palm OS, Symbian OS, Windows mobile
Secure applications
Bandwidth Requirements for Various
Peripheral Technologies

Peripheral Technical Required Bandwidth

Graphics 24-bit color 30 MBytes/sec
Local area network 100BASEX or FDDI 12 Mbytes/sec
Disk controller SCSI or P1394 10 Mbytes/sec
Full-motion video 1024 x 768@30fps 67+ Mbytes/sec
I/O Peripherals Other miscellaneous 5+ Mbytes/sec