Basic architecture of input-output processor (IOP)

- It is a processor with direct memory access capability that communicates with input-
output devices.
- Input-output processor except that it is designed to handle the details of input-output
operations.
- Unlike DMA which is initialized by CPU, input-output processor can fetch and execute its
own instructions.
-

CPU

MEMORY UNIT
Address bus

PD
PD PD PD

IOP

Peripheral devices

Block diagram of computer with input-output processor

- Memory occupies the central position and can communicate with each processor by
DMA.
- CPU is responsible for processing data.
- Input-output processor provides the path for transfer of data between various
peripheral devices and memory.
- Data formats of peripherals different from CPU and memory. Input-output processor
maintains such problems.
- Data are transfer from input-output to memory by stealing one memory cycle.
- Instructions that are read from memory by input-output processor are called commands
to distinguish them from instructions that are read by the CPU.
CPU operations input output operations

Send information to test

input output processor
path Transfer status word to memory
location

If status ok, send start

input output instructions
to input output processor Access memory for input output
processor program

CPU continuous with

another program Conduct input output transfers
using DMA; prepare status report

Request input output Input output transfer

processor status completed CPU

Transfer status word to

Check status word for memory location
correct transfer
 Instructions that are read from memory by an input output processor.

- Distinguish from instructions that are read by the CPU.

- Commands are prepared by experienced programmers and are stored in memory.
- Command word = input output program.

Performed by the control circuit i.e. part of input output device interface.

The unit communicates with the CPU via a data bus and control lines.

The RD and WR lines are bidirectional when BG is equal to zero the CPU can communicates
with DMA registers through data bus to read from or write to DMA registers. When BG is
equal to one the CPU is relinquished. The bus can communicate directly with the memory
by specifying the address in the address bus and activating the read or write control.

The DMA controller has three registers.

Architecture of DMA

In the direct memory access (DMA) the interface transfer the data into and out of
the memory unit through the memory bus. The transfer of data between a fast
storage device such as magnetic disk and memory is often limited by the speed of
the CPU. Removing the CPU from the path and letting the peripheral device
manage the memory buses directly would improve the speed of transfer. This
transfer technique is called direct memory access (DMA).

The CPU may be placed in an idle state in a variety of ways. One common method
extensively used in microprocessor is to disable the buses through special control
signals such as:

 Bus request (BR)

 Bus grant (BG)

These two control signals in the CPU that facilitates the DMA transfer. The bus
request (BR) input is used by the DMA controller to request the CPU. When this
input is activate, the CPU terminates the execution of the current instruction and
places the address bus, data bus and read write lines into a high impedance state.
High impedance state means that the output is disconnected.

BR ABUS
Bus request Address bus
High impedance (disable) DBUS
Data bus
when BG is enable. RD
Read
WR
Bus grant write
BG

CPU bus signal for DMA transfer

The CPU activates the bus grant (BG) output to inform the external DMA that the bus request
(BR) can now take control to the buses to conduct memory transfer without processor.

The transfer can be made in several ways that are:

 DMA burst- in this a block sequences consisting of a number of memory words

are transferred in a continuous burst. While the DMA controller is the master of
the buses.
 Cycle stealing- in this stealing the DMA controller one data words at a time
after which it must return, the control of buses to the CPU. The CPU merely
delays its operation for one memory cycle to allow the direct memory input
output transfer to steal one memory cycle.

DMA Controller

The DMA controller needs the usual circuits of an interface to communicate with the CPU and
input output device. The DMA controller has three registers:

a) Address register
b) Word count register
c) Control register

Address register: address register contains an address to specify the desired location in
memory.
Word count register: WC holds the number of words to be transferred. The register is
increment/decrement by one after each word transfer and internally tested for zero.

Control register: control register specifies the mode of transfer

The unit communicates with the CPU via the data bus and the control lines. The registers in the
DMA are selected by the CPU through the address bus by enabling the DS (DMA select) and RS
(register select) inputs. The RD (read) and WR (write) inputs are bidirectional.

When the BG (bus grant) input is 0, the CPU can communicate with the DMA registers through
the data bus to read from or write to the DMA registers. When BG =1, the DMA can
communicate directly with the memory by specifying an address in the address bus and
activating the RD or WR control.
DMA Transfer

 When peripheral device sends a DMA request the DMA controller activate the
BR lines informing CPU. To relinquish the control of buses.
  CPU initializes the DMA and respond by BG line.
 DMA puts them the correct value of address register into the address bus,
initiate the read or write signal and send DMA acknowledge to the peripheral
device.
 RD and WR are bidirectional. The direction of transfer of depends on the status
of BG lines.
 When BG is equal to zero RD and WR are input lines allowing CPU to
communicate with the internal DMA register.
 When BG is equal to 0 RD and WR are output line from DMA controller to RAM
to specify the read or write operation of data.
 For each word transfer the DMA increments its address register and decrement
it control count register.
 If the control word is not zero the DMA check the request line coming from the
peripheral for a high speed device the line will be activate as soon as the
previous transfer is completed. The second transfer is then initiated and the
process continuous until the entire block is transferred. The zero indicates all
words transfer successfully.

Modes of data transfer

Transfer of data is required between CPU and peripherals or memory or

sometimes between any two devices or units of computer system. To transfer a
data from one unit to another one should be sure that both units have proper
connection and at the time of data transfer the receiving unit is not busy. The
data transfer with the computer is internal operation.

The data transfer can be handled by various modes. Some of the modes use CPU
as an intermediate path, others transfer data directly to and from the memory
unit and this can be handled by 3 following ways:

a) Programmed I/O Mode: in this mode of data transfer the operations are the
results in input output instructions which are a part of computer program.
Each data transfer is initiated by a instructions in the program. Normally the
transfer is from a CPU register to peripheral device or vice-versa.

Once the data is initiated the CPU starts monitoring the interface to see
when next transfer can make. The instructions of the program keep close
 tabs on everything that takes place in the interface unit and the input output
devices.

The transfer of data requires three instructions:

a) Read the status register.

b) Check the status of the flag bit and branch to step 1 if not set or to step 3 if
set.
c) Read the data register.
B) Interrupt-initiated I/O: in this method an interrupt facility an interrupt
command is used to inform the device about the start and end of transfer.

When the COU receives such signal, it temporarily stops the execution of the
program and branches to a service program to process the input output transfer
and after completing it returns back to task, what it was originally performing.

 In this type of input-output, computer does not check the flag, it

continue to perform its task.
 Whenever any device wants the attention, it sends the interrupt
signal to the CPU.
 CPU then deviates from what it was doing, store the return address
from PC and branch to the address of the subroutine.
 There are two ways of choosing the branch address:
 a) Vectored interrupt
b) Non-vectored address
 In vectored interrupt the source that interrupts the CPU provides
the branch information. This information is called interrupt
vectored.
 In non-vectored interrupt, the branch address is assigned to the
fixed address in the memory.

c) Direct memory access:

Input output interface

Input output interface provides a method for transferring information between

internal storage and external input-output devices.

Peripheral connected to a computer need special communication links for

interfacing them with the central processing unit.

The purpose of communication link is to resolve the differences that exist

between the central compute and each peripheral.

The major differences are:

1. Peripheral and electromechanical and electronic magnetic devices and CPU

and memory are electronic devices. Therefore, a conversion of signal values
may be needed.
2. The data transfer rate of peripherals is usually slower than the transfer rate
of CPU and consequently, a synchronization mechanism may be needed.
3. Data codes and formats in the peripherals differ from the word format in
the CPU and memory.

To resolve these differences, computer systems include special hardware

components between the CPU and peripherals to supervise and synchronize all
input and out transfers.
  These components are called interface units because they interface
between the processor bus and the peripheral devices.

I/O BUS and Interface Module

It defines the typical links between the processor and several peripherals.

The I/O bus consists of data lines, address lines and control lines.

The I/O bus from the processor is attached to all peripheral interfaces.

To communicate with a particular device, the processor places a device address

on address lines.

Each interface decodes the address and control received from the I/O bus,
interprets them for peripherals and provides signals for the peripheral controller.

It is also synchronize the data flow and supervises the transfer between
peripheral and processor.

Each peripheral has its own controller.

For example: the printer controller controls the paper motion, the print timing.

The control lines are referred as I/O command. The commands are as following:

Control command- A control command is issued to activate the peripheral and to

inform it what to do.

Status command- a status command is used to test various status conditions in

the interface and the peripheral.

Data output command- A data output command causes the interface to respond
by transferring data from the bus into one of its registers.

Data input command- the data input command is the opposite of the data output.

In this case the interface receives on items of data from the peripheral and places
it in its buffer register. I/O versus memory bus.
 To communicate with the I/O, the processor must communicate with the memory unit.
Like the I/O bus, the memory bus contains data, address and read/write control lines.
There are three ways that computer can used to communicate with memory and I/O:
a) Us two separate buses, one for memory and other for I/O.
b) Use one common bus for both memory and I/O but separate control lines for each.
c) Use one common bus for memory and I/O with common control lines.

Priority interrupt
There are number of input output devices attached to the computer.

They are capable of generating the interrupt.

When the interrupt is generated from more than one device, priority interrupt system is used
to determine which device is to be serviced first.

Devices with high speed transfer are given higher priority and slow devices are given lower
priority.
Establishing the priority can be done in two ways:

 Using software
 Using hardware

A polling procedure is used to identify highest priority in software means.

Polling procedure:
There is one common branch address for all interrupts.

Branch address contains the code that polls the interrupt sources in sequence. The highest
priority is tested first.

The particular service routine of the highest priority device is served.

The disadvantage is that time required to poll them can exceed the time to serve them in large
number of I/O devices.

Using hardware:
Hardware priority system functions as an overall manager.

It accepts interrupt request and determine the priorities.

To speed up the operation each interrupting device has its own interrupt vector.

No polling is required; al decisions are established by hardware priority interrupt unit.

It can be established by serial or parallel connections of interrupt lines.

Serial or Daisy chaining priority:

Device with highest priority is placed first.

Device that wants the attention send the interrupt request to the CPU.

CPU then sends the INTACK signal which is applied to PI (priority in) of the first device.
If it had requested the attention, it place in VAD (vector address) on the bus. And it block the
signal by placing 0 in PO (priority out).

If not it pass the signal to next device through PO (priority out) by placing 1.

This process is continued until appropriate device is found.

The device whose PI is 1 and PO is 0 is the device that send the interrupt request.

Parallel priority interrupt

it consist of interrupt register whose bits are set separately by the interrupting deviced.

Priority is established according to the position of the bits in the register.

Mask register is used to provide facility for the higher priority devices to interrupt when lower
priority device is being serviced or disable all lower priority devices. When higher is being
serviced.

Corresponding serviced bit and mask bit are ANDed and applied to priority encoder.

Priority encoder generates two bits of vector address.

Another output form it sets IST (interrupt status flip flop)

The execution process of interrupt initiated input output is represented in the flow chart.
Asynchronous data transfer :
The scheme is used when input output devices do not match with microprocessor, and timing
characteristics of input output devices is not predictable.

In this method, process initiates the device and checks its status. As a result, CPU has to wait till
input output device is ready to transfer data. When device is ready CPU issues instruction for
input output transfer. In this method two types of techniques are used based on signals before
data transfer.

a) Strobe control
b) Handshaking
 Strobe control: the strobe control method of asynchronous data transfer
employs a single control line to time each transfer. The strobe may be activated
by either the source or the destination unit.

Data transfer initiated by source unit:

Disadvantage of strobe signal:

the disadvantage of the strobe method is that, the source unit initiates the transfer has no way
of knowing whether the destination unit has actually received the data item that was places in
the bus. Similarly, a destination unit that initiates the transfer has no way of knowing whether
the source unt has actually placed the data on bus. The handshaking method solve this
problem.

Handshaking
the handshaking method solve the problem of strobe method by introducing a second control
signal that provides a reply to the unit that initiates the transfer.

Source initiated transfer using handshaking

The sequence of events shows four possible states that the system can be at any given time.
The source unit initiates the transfer by placing the data on the bus and enabling its data valid
signal. The data accepted signal is activated by the destination unit after it accepts the data
from the bus. The source unit then disables its data accepted signal and the system goes inot its
initial state.
Destination initiated transfer using handshaking
The name of the signal generated by the destination unit has been changed to ready for data to
reflect its new meaning. The source unit in this case does not place data on the bus until after it
receives the ready for data signal from the destination unit. From there on, the handshaking
procedure follows the same pattern as in the source initiated case.
The only difference between the source initiated and the destination initiated transfer is in their
choice of initial state.
Advantage of handshaking method:

A) The handshaking scheme provides degree of flexibility and reliability because the
successful completion of data transfer relies on active participation by both units.
B) If any of one unit is faulty, the data transfer will not be completed. Such an error can by
detected by means of a timeout mechanism which provides an alarm if the data is not
completed with time.

Synchronous data transfer

The start and stop bits in each frame of asynchronous format represents wasted overhead
bytes that reduce overall character rate.

These start and stop bits can be eliminated by synchronizing receiver and transmitter.

They can be synchronized by having a common clock signal.

Such a communication is called synchronous serial communication.

In this transmission synchronous bits are inserted instead of start and stop bits.

The data rate can be expressed as bit/sec or character/sec.

The term bit/sec is also called baud rate.

Difference between serial and parallel communication

Serial communication:

 most of microprocessor are designed for parallel communication.

 In parallel communication number of lines required to transfer data depends on
the number of bits to be transmitted.
 For transmitting data over long distance, using parallel communication is
impractical due to the increase in cost of cabling.
  In such cases serial communication is used.
 In serial communication one bit is transferred at a time over a single line.
 Serial communication can be classified on the basis how transmission occurs.
 Simple: in simplex, the hardware such that data transfer takes place in only one
direction.
Ex. Computer to printer communication
 Half duplex: the half duplex transmission allows the data transfer in both
direction but not simultaneously.
Ex. Walkie talkie
 Full duplex: it allows the data transfer in both direction simultaneously.
Ex. Telephone lines

Parallel communication
Parallel communication is a method of conveying multiple binary digits (bits) simultaneously, it
contrast with serial communication, which conveys only a single bit at a time.

The basic difference between them is the number of electrical conductors used at the physical
layer to convey bits in communication.

Peripheral devices
The input/output organization of computer depends upon the size of computer and the
peripheral connected to it. The input/output subsystem of the computer, provides and efficient
mode of communication between the central system and the outside environment.

The most common input output devices are:

a) Monitor
b) Keyboard
c) Mouse
d) Printer
e) Magnetic tapes

Peripheral devices that provide auxiliary storage for the system are magnetic disks and
magnetic tapes.

1. Monitors: monitors are the most popular output devices used today for producing soft-
copy output. A monitor displays information in visual form, using text and graphics. We
can see pictures and videos on a monitor. So it is called as VDU (visual display unit).
There are two types of monitors
a) CRT (cathode Ray tube) monitors and
b) LCD (liquid crystal display) monitors

Both types produce sharp image, but LCD monitors have the advantage that they are
much thinner and lighter as compared to CRT monitors.

CRT monitors look much like a television and are used with non-portable computer
systems. CRT monitors are available in monochrome (i.e. black and white) and color.

The flat panel monitors (like LCDs and TFTs) are thinner, lighter and consume low
energy. LCD stands for liquid crystal display. TFT stands for thin film transistor. LCDs are
commonly used with portable computer systems (like laptop computers), watches and
calculations.

Keyboard: whether you are writing a letter or entering numerical data, keyboard is the
main way to enter information into your computer. Keyboard is an indirect entry device.
Keyboard come in a variety of sizes and shapes but most keyboards used with computer
systems have a certain number of keys which are very common: typing (alphanumeric)
keys, control keys, function keys, navigation keys and numeric keypad.

Printers: printers are the most commonly used output devices for producing hard-copy
output. A printer transfer data from a computer onto paper. Some printers produce only
letters and numbers whereas other can also produce graphics.

Many people can also print their own photos at home using special type of printers.

Printers are broadly classified into two types:

Impact printers: An impact printer prints the characters by using a hammer or pins to
strike an ink ribbon against the face of a continuous paper.

Impact printers can further classified into two classes

a) Character printers: these printers print one character of the text at a time.
Two types of character printer are available:
Dot-matrix printer
Daisy wheel printer
b) Line printers: A line printer prints one line at a time. It is very fat output device. The
printing speed lies in the range of 600-6000 lines per minute. It is used for large
volume printing jobs. It may be used with mini and large computers.
 Non-impact printer: printers that don’t strike hammers against ribbon or paper when
they print are termed as non impact printers. These printers generate much less noise
as compared to the impact printers do. Some non impact printers are described below:

a) Laser printer: it is a page printer, which print one page at a time. It has laser beam
source, a multi-sided mirror, a photoconductive drum and a toner.
b) Inkjet printer: its are character printers, which form characteristics and all kinds of
images by spraying small drops of ink on the paper.

Magnetic tape

Magnetic tape is an example of secondary memory. Magnetic tape is one of the most popular
storage mediums for storing large amount of data that can be accessed and processed
sequentially. The tape ribbon itself is stored in reels of 50 to 2400 feet’s or a small cartridge or
cassette. When we record new data on a tape, old data (in the same area) get automatically
erased.

Magnetic disks

Magnetic disk is an example of secondary memory. Magnetic dish is the most popular medium
for direct access secondary storage. A magnetic disk is a thin, circular metal plate coated on
both sides with a magnetized material, such as iron oxide. This disk preserves the information
even when the computer is turned off. For data recording, the surface of a disk is divided into a
number of invisible circles, called tracks. The number of tracks varies greatly between disks,
from 40 to several thousands.

Hard disks

Hard disk are the secondary storage devices used in most computer systems today. They are
made of light metal (frequency aluminum). Information is recorded on the hard disk in the form
of tiny invisible magnetized and non magnetized spots. Hard disk drive is used to write and read
the information on a hard disk. As hard disk can hold massive amounts of information, they
usually serve as your computer’s primary means of storage, holding almost all of your programs
and files. Hard disk is used to store, operating=g system, application software and other files.

Memory

Computer storage has storage areas, often referred to as memory. Memory is one of the
important components of the computer hardware. The memory can receive, hold and deliver
data when instructed to do so. Two types of memory used in computer are:
 1) Primary memory: it is also known as working memory, main memory, primary storage
and internal storage. It is capable of sending and receiving the data at very high speed. It
has faster access time but smaller storage capacity as compared to secondary memory.
The main memory capacity is defined in terms of number of bytes a computer system
can store. It is normally stated in terms of KB (kilobyte), MB (megabyte), GB (gigabyte).
Some of the primary memories are: RAM and ROM.
2) Secondary memory: secondary memory is also called long-term memory, auxiliary
memory, backup storage and secondary storage. It store data not currently being used.
This form of storage store s the data permanently in the given media. Its operating
speed is slower than that of the primary storage. Cost per bit is low as compared to
primary storage. Magnetic tapes, hard disk, optical disk, pen drive etc. are some
secondary storage devices.

RAM (random access memory)

RAMs consists of electronic circuits prepared on silicon chips. It is also known as read/write
memory. RAM Is volatile in nature. It means contents of the RAM will be lost after switching off
the computer. RAM is usually installed into sockets situated on the motherboard of the
microcomputer as DIMMs (dual inline memory module), which is a small circuit boards that
holds the RAM chips. In today’s computers ram size is measured in MB and GB. A typical micro
computer in 2010 might have 2 GB of RAM installed.

Show the block diagram of RAM. It has n input lines, which provides the information to be
stored in memory. It has n output lines, which supply the information coming out of the
memory. It has k address lines, which provide a binary information of k bits that specify a
particular word chosen among the 2^k available inside the memory. It has two control inputs
(read and write), the write signal specifies a transfer-in operation and the read signal specifies a
transfer-out operation. According to one of these signals, the internal circuits inside the
memory provide the desired function.

a) Static RAM: static RAM retains stored information only as long as the power supply is
on. They are used where large capacity of memory is needed. Static RAM is costlier and
consumes more power. SRAM do not need circuitry. They have higher speed than
dynamic RAMs. Static RAM being faster is used cache memory. Static RAM use CMOS
technology. CMOS device consumes less power. Static RAM hold information in a flip
flop circuit consisting of two cross inverters. Six transistors are needed, per memory cell
in static RAM.
b) Dynamic RAM: dynamic RAM loses its stored information in a very short time (a few
milliseconds) even though the power supply is on. Therefore the dynamic RAM have to
be refreshed periodically, generally every 2 milliseconds, in dynamic RAM are cheaper
 and higher packing density and moderate speed. They consume less power. they are
used where large capacity of memory is needed. DRAM uses CMOS technology.
Dynamic RAM requires less number of transistors per memory cell because information
is stored on stray capacitors. Only one transistor is needed to form a memory cell of the
dynamic RAM.