Direct memory access with DMA

controller 8257/8237
Suppose any device which is connected at input-output port wants to transfer data to
memory, first of all it will send input-output port address and control signal, input-
output read to input-output port, then it will send memory address and memory write
signal to memory where data has to be transferred. In normal input-output technique
the processor becomes busy in checking whether any input-output operation is
completed or not for next input-output operation, therefore this technique is slow.
This problem of slow data transfer between input-output port and memory or between
two memory is avoided by implementing Direct Memory Access (DMA) technique.
This is faster as the microprocessor/computer is bypassed and the control of address
bus and data bus is given to the DMA controller.
 HOLD – hold signal
 HLDA – hold acknowledgment
 DREQ – DMA request
 DACK – DMA acknowledgment

Suppose a floppy drive which is connected at input-output port wants to transfer data
to memory, the following steps are performed:
 Step-1: First of all the floppy drive will send DMA request (DREQ) to the
DMAC, it means the floppy drive wants its DMA service.
 Step-2: Now the DMAC will send HOLD signal to the CPU.
 Step-3: After accepting the DMA service request from the DMAC, the
CPU will send hold acknowledgement (HLDA) to the DMAC, it means the
microprocessor has released control of the address bus the data bus to
DMAC and the microprocessor/computer is bypassed during DMA service.
  Step-4: Now the DMAC will send one acknowledgement (DACK) to the
floppy drive e=which is connected at the input-output port. It means the
DMAC tells the floppy drive be ready for its DMA service.
 Step-5: Now with the help of input-output read and memory write signal
the data is transferred from the floppy drive to the memory.
Modes of DMAC:

1. Single Mode – In this only one channel is used, means only a single
DMAC is connected to the bus system.

2. Cascade Mode – In this multiple channels are used, we can further cascade
more number of DMACs.

Introduction of 8237

 Direct Memory Access (DMA) is a method of allowing data to be moved from one
location to another in a computer without intervention from the central processor (CPU).
 It is also a fast way of transferring data within (and sometimes between) computer.
 The DMA I/O technique provides direct access to the memory while the microprocessor is
temporarily disabled.
 The DMA controller temporarily borrows the address bus, data bus and control bus from
the microprocessor and transfers the data directly from the external devices to a series of
memory locations (and vice versa).

Basic DMA Operation:

  Two control signals are used to request and acknowledge a direct memory access (DMA)
transfer in the microprocessor-based system.
1. The HOLD signal as an input(to the processor) is used to request a DMA action.
2. The HLDA signal as an output that acknowledges the DMA action.
 When the processor recognizes the hold, it stops its execution and enters hold cycles.
 HOLD input has higher priority than INTR or NMI.
 The only microprocessor pin that has a higher priority than a HOLD is the RESET pin.
 HLDA becomes active to indicate that the processor has placed its buses at high-
impedance state.

Basic DMA Definitions

 Direct memory accesses normally occur between an I/O device and memory without the
use of the microprocessor.
1. A DMA read transfers data from the memory
to the I/O device.
2. A DMA write transfers data from an I/O device
to memory.
 The system contains separate memory and I/O control signals.
 Hence the Memory & the I/O are controlled simultaneously
 The DMA controller provides memory with its address, and the controller signal selects
the I/O device during the transfer.
 Data transfer speed is determined by speed of the memory device or a DMA controller.
 In many cases, the DMA controller slows the speed of the system when transfers occur.
 The serial PCI (Peripheral Component Interface) Express bus transfers data at rates
exceeding DMA transfers.
 This in modern systems has made DMA is less important.

CPU having the control over the bus

When DMA operates

The 8237 DMA Controller
 The 8237 supplies memory & I/O with control signals and memory address information
during the DMA transfer.
 It is actually a special-purpose microprocessor whose job is high-speed data transfer
between memory and I/O

 8237 is not a discrete component in modern microprocessor-based systems.

 It appears within many system controller chip sets
 8237 is a four-channel device compatible with 8086/8088, adequate for small systems.
 Expandable to any number of DMA channel inputs
 8237 is capable of DMA transfers at rates up to 1.6MB per second.
 Each channel is capable of addressing a full
64K-byte section of memory.