Digital Design and Computer Architecture: ARM® Edition: Sarah L. Harris and David Money Harris

Chapter 7
Digital Design and Computer Architecture: ARM® Edition

Sarah L. Harris and David Money Harris
Digital Design and Computer Architecture: ARM® Edition © 2015 Chapter 7 <1>
Chapter 7 :: Topics
• Introduction
• Performance Analysis
• Single-Cycle Processor
• Multicycle Processor
• Pipelined Processor
• Advanced Microarchitecture
Introduction
• Microarchitecture: how to
implement an architecture
in hardware
• Processor:
– Datapath: functional blocks
– Control: control signals
Microarchitecture
• Multiple implementations for a single
architecture:
– Single-cycle: Each instruction executes in a
single cycle
– Multicycle: Each instruction is broken up into
series of shorter steps
– Pipelined: Each instruction broken up into series
of steps & multiple instructions execute at once
Processor Performance
• Program execution time
Execution Time = (#instructions)(cycles/instruction)(seconds/cycle)
• Definitions:
– CPI: Cycles/instruction
– clock period: seconds/cycle
– IPC: instructions/cycle = IPC
• Challenge is to satisfy constraints of:
– Cost
– Power
– Performance
ARM Processor
• Consider subset of ARM instructions:
– Data-processing instructions:
• ADD, SUB, AND, ORR
• with register and immediate Src2, but no shifts
– Memory instructions:
• LDR, STR
• with positive immediate offset
– Branch instructions:
• B
Architectural State Elements
Determines everything about a processor:
– Architectural state:
• 16 registers (including PC)
• Status register
– Memory
ARM Architectural State Elements
CLK
4 4
CLK
Status CLK
CLK WE3
A1 RD1 WE
4 32
PC' PC
A RD A RD
32 32 32 32 A2 RD2 32 32
Instruction
4 32 Data
Memory A3 Register Memory
4
WD3 File WD
32 32
R15
32
Single-Cycle ARM Processor
• Datapath
• Control
• Datapath
• Control
• Datapath: start with LDR instruction
• Example: LDR R1, [R2, #5]
LDR Rd, [Rn, imm12]
Single-Cycle Datapath: LDR fetch
STEP 1: Fetch instruction
CLK CLK
CLK
Instr
WE3 WE
PC' PC A1 RD1
A RD
A RD
Instructi on A2 RD2
Memory Data
Memory
A3 Register
WD
WD3 File
R15
Single-Cycle Datapath: LDR Reg Read
STEP 2: Read source operands from RF
CLK CLK
CLK
PC' PC Instr 19:16 RA1

A1
WE3
RD1
WE
A RD
A RD
Instruction A2 RD2
Memory Data
Memory
A3 Register
WD
WD3 File
R15
LDR Rd, [Rn, imm12]
Single-Cycle Datapath: LDR Immed.
STEP 3: Extend the immediate
CLK CLK
CLK
Instr
19:16 RA1 WE3 WE
PC' PC A1 RD1
A RD
A RD
Instructi on A2 RD2
Memory Data
15:12 Memory
A3 Register
WD
WD3 File
R15
11:0
Extend ExtImm
LDR Rd, [Rn, imm12]
Single-Cycle Datapath: LDR Address
STEP 4: Compute the memory address
ALUControl
00
CLK CLK
CLK
Instr
19:16 RA1 WE3 SrcA WE
PC' PC A1 RD1
A RD ALUResult
ALU
A RD
Instructi on A2 RD2 SrcB Data
Memory
15:12 Memory
A3 Register
WD
WD3 File
R15
11:0
Extend ExtImm
LDR Rd, [Rn, imm12]
Single-Cycle Datapath: LDR Mem Read
STEP 5: Read data from memory and write it
back to register file RegWrite ALUControl
1 00
CLK CLK
CLK
Instr

PC' PC A1 RD1
A RD ALUResult ReadDat a
ALU
A RD
Instructi on A2 RD2 SrcB Data
Memory
15:12 Memory
A3 Register
WD
WD3 File
R15
11:0
Extend ExtImm
LDR Rd, [Rn, imm12]
Single-Cycle Datapath: PC Increment
STEP 6: Determine address of next instruction
RegWrite ALUControl
1 00
CLK CLK
CLK
Instr
o
PC' PC A1 RD1
A RD ALUResult ReadData
ALU
A RD
Instruction A2 RD2 SrcB Data
Memory
15:12 Memory
A3 Register
WD
WD3 File
R15
PCPlus4
+
4
11:0
Extend Ext Imm
Single-Cycle Datapath: Access to PC
PC can be source/destination of instruction
PCSrc RegWrite ALUControl

1 1 00
CLK CLK
CLK
Instr

1 PC' PC A1 RD1
0
ALU
A RD
Memory
15:12 Memory
A3 Register
WD
WD3 File
4
PCPlus8
R15
+
PCPlus4
+
4
11:0
Extend ExtImm
• Source: R15 must be available in Register File
– PC is read as the current PC plus 8

1 1 00
CLK CLK
CLK
Instr

1 PC' PC A1 RD1
0
ALU
A RD
Memory
15:12 Memory
A3 Register
WD
WD3 File
4
PCPlus8
R15
+
PCPlus4
+
4
11:0
Extend ExtImm
• Source: R15 must be available in Register File
– PC is read as the current PC plus 8
• Destination: Be able to write result to PC
1 1 00
CLK CLK
CLK
Instr

1 PC' PC A1 RD1
0
ALU
A RD
Memory
15:12 Memory
A3 Register
WD
WD3 File
4
PCPlus8
R15
+
PCPlus4
+
4
11:0
Extend ExtImm
Single-Cycle Datapath: STR
Expand datapath to handle STR:
• Write data in Rd to memory
PCSrc RegWrite ALUControl MemWrite
0 0 00 1
CLK CLK
CLK
Instr WE3 WE
19:16 RA1 SrcA
1 PC' PC A1 RD1
ALU
0 A RD
Instruction RA2
A2 RD2 SrcB Data
Memory
15:12 Memory
A3 Register WriteData
WD
WD3 File
4
PCPlus8
R15
+
PCPlus4
+
4
11:0
Extend ExtImm
STR Rd, [Rn, imm12]
Single-Cycle Datapath: Data-processing
With immediate Src2:
• Read from Rn and Imm8 (ImmSrc chooses the zero-extended Imm8
instead of Imm12)
• Write ALUResult to register file
• Write to Rd
ADD Rd, Rn, imm8
With immediate Src2:
• Read from Rn and Imm8 (ImmSrc chooses the zero-extended Imm8
instead of Imm12)
• Write to Rd
PCSrc RegWrite ImmSrc ALUControl MemtoReg
ALUFlags
MemWrite
0 1 0 varies 0 0
CLK CLK
CLK
Instr

1 PC' PC A1 RD1
ALU
0 A RD
Instructi on RA2
A2 RD2 SrcB Data
Memory
15:12 Memory
WD
WD3 File
4 1
PCPlus8
R15
+
PCPlus4 0
+
4
11:0
Extend ExtImm
Result
ADD Rd, Rn, imm8
With register Src2:
• Read from Rn and Rm (instead of Imm8)
• Write to Rd
ADD Rd, Rn, Rm
With register Src2:
• Read from Rn and Rm (instead of Imm8)
• Write to Rd
PCSrc RegSrc RegWrite ImmSrc ALUSrc ALUControl MemtoReg
ALUFlags
MemWrite
0 0 1 X 0 v aries 0 0
CLK CLK
CLK
Instr

1 PC' PC A1 RD1
ALU
0 3:0 A RD
Instruction 0 RA2
A2 RD2 0 SrcB Data
Memory 1
15:12 1 Memory
WD
4 WD3 File
PCPlus8 1
R15
+
PCPlus4 0
+
4
11:0
Extend ExtImm
Result
ADD Rd, Rn, Rm
Single-Cycle Datapath: B
Calculate branch target address:
BTA = (ExtImm) + (PC + 8)
ExtImm = Imm24 << 2 and sign-extended
ALUFlags
MemWrite
1 1 x 0 10 1 00 0 0
CLK CLK
CLK
19:16
Instr
0 RA1 WE3 SrcA WE
1 PC' PC A1 RD1
A RD 15 1 ALUResult ReadData
ALU
0 3:0 A RD
Instruction 0 RA2
A2 RD2 0 SrcB Data
Memory 1
15:12 1 Memory
WD
WD3 File
4 1
PCPlus8
R15
+
PCPlus4 0
+
4
23:0
Extend Ext Imm
Result
B Label
Single-Cycle Datapath: ExtImm
ALUFlags
MemWrite
1 1 x 0 10 1 00 0 0
CLK CLK
CLK
19:16
Instr
0 RA1 WE3 SrcA WE
1 PC' PC A1 RD1
ALU
0 3:0 A RD
Instructi on 0 RA2
A2 RD2 0 SrcB Data
Memory 1
15:12 1 Memory
WD
4 WD3 File
PCPlus8 1
R15
+
PCPlus4 0
+
4
23:0
Extend ExtImm
Result
ImmSrc1:0 ExtImm Description

00 {24’b0, Instr7:0} Zero-extended imm8
01 {20’b0, Instr11:0} Zero-extended imm12
10 {6{Instr23}, Instr23:0, 00} Sign-extended imm24
PCSrc
Control
MemtoReg
Unit
31:28 MemWrite
Cond
27:26 ALUControl
Op
25:20 ALUSrc
Funct
15:12
Rd ImmSrc
RegWrite
Flags
ALUFlags
RegSrc
0 1 CLK CLK
CLK
19:16
Instr
0 RA1 WE3 SrcA WE

1 PC' PC A1 RD1
ALU
0 3:0 A RD
Instructi on 0 RA2
A2 RD2 0 SrcB Data
Memory 1
15:12 1 Memory
WD
4 WD3 File
PCPlus8 1
R15
+
PCPlus4 0
+
4
23:0
Extend Ext Imm
Result

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Chapter 7

Digital Design and Computer Architecture: ARM® Edition

PC' PC Instr 19:16 RA1

LDR Rd, [Rn, imm12]

LDR Rd, [Rn, imm12]

LDR Rd, [Rn, imm12]

19:16 RA1 WE3 SrcA WE

LDR Rd, [Rn, imm12]

PCSrc RegWrite ALUControl

19:16 RA1 WE3 SrcA WE

PCSrc RegWrite ALUControl

19:16 RA1 WE3 SrcA WE

19:16 RA1 WE3 SrcA WE

STR Rd, [Rn, imm12]

ADD Rd, Rn, imm8

19:16 RA1 WE3 SrcA WE

ADD Rd, Rn, imm8

ADD Rd, Rn, Rm

PCSrc RegSrc RegWrite ImmSrc ALUSrc ALUControl MemtoReg

19:16 RA1 WE3 SrcA WE

ADD Rd, Rn, Rm

ImmSrc1:0 ExtImm Description

0 RA1 WE3 SrcA WE

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