Code: R7310404

R07
(Electronics and Communication Engineering)

B.Tech III Year I Semester (R07) Supplementary Examinations December/January 2013/14 DIGITAL IC APPLICATIONS Time: 3 hours Answer any FIVE questions All questions carry equal marks *****
1 (a) (b) 2 (a) (b) Draw the logic diagram equivalent to the internal structure of an 8-input CMOS NAND gate. Show the transistor circuit for this gate and explain the operation with the help of function table. Draw the circuit diagram of a two-input LS-TTL NOR gate and explain the functional behavior. Design a three input NAND gate using diode logic and a transistor inverter. Analyze the circuit with the help of transfer characteristics. Explain the behavioral design model of VHDL. Design the logic circuit and write a data-flow style VHDL program for the following function: F (X) = A,B,C,D (3, 5, 6, 7, 13) + d(1, 2, 4, 12, 15) Explain data-flow design elements of VHDL. Write a data-flow style VHDL program for the following functions: F(S) = A B CI F(C0) = AB + ACI + BCI Draw the structure of a 4-bit comparator and briefly explain about it. Write a structural VHDL code for it. Discuss about a 4-bit comparator with the relevant equations. Give the logic symbol for 74X85and write a VHDL. Determine fmax for the 4 bit synchronous counter if tpd for each flip-flop is 50 ns and tpd for AND gate is 20 ns. Compare this with fmax for a MOD 16 ripple counter. Draw the basic structure of a ROM and explain the operation with a truth table. Briefly explain 2-4 decoder using an 8X4 ROM.

Max Marks: 80

3 (a) (b)

4 (a) (b)

8 (a) (b)

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