Code: R5310404 R5

B.Tech III Year I Semester (R05) Supplementary Examinations, November 2012

DIGITAL IC APPLICATIONS
(Common to ECE and EIE)
Time: 3 hours Max Marks: 80
Answer any FIVE questions
All questions carry equal marks
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1 (a) Design a CMOS circuit that has the functional behavior shown
A o o
o Z .
Bo
Co
(b) Explain the dynamic electrical behavior of CMOS circuits.

2 (a) Draw and explain? Input ECL NAND logic circuit and its functional table.
(b) Give the electrical static behavior of TTL circuits.

3 (a) Give the syntax for package, package declaration and package body and compare this with
libraries.
(b) Give the sketch of VHDL design flow and explain.

4 (a) List the types of VHDL models and explain one example each.
(b) Explain simulation and synthesis.

5 (a) Write a VHDL code for 4-to-16 binary decoder using entity architecture configuration.
(b) What are the advantages and disadvantages of test bench and wave form editor.

6 (a) Design a 8 bit shift resistor which shifts from left to right and takes parallel load write its
VHDL lode and use assert statement.
(b) Design a D Flip-Flop using wait statements.

7 (a) Design a 4 bit comparator in a sequential model.

(b) Write a VHDL code for dual parity encodes.

8 (a) Give the internal ROM structure and timing explain.

(b) Compare the SRAMs and DRAMs.

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