R07

Code: R7221004

B.Tech II Year II Semester (R07) Supplementary Examinations May/June 2015

DIGITAL IC APPLICATIONS
(Electronics and Instrumentation Engineering)

Time: 3 hours Max. Marks: 80

Answer any FIVE questions
All questions carry equal marks
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1 (a) Explain IC interfacing for CMOS and TTL family.
(b) Draw and explain the logic diagram for inverter using CMOS logic.

2 (a) Write and description of the following ICS:

(i) 74 LS 00. (ii) 74 HS 00. (iii) 74 LS 32.
(b) Compare TTL, MOS & ECL logic families in detail.

3 (a) Describe object classes and object types used in VHDL language.
(b) What is the purpose of the type STD_ULOGIC?
(c) What is scalar type? List the predefined scalar types. Where are these predefined types declared?

4 (a) List and define the five kinds of VHDL types, which types are used in design descriptions for
synthesis? Where might the other types be used?
(b) What kind of statements make up a data flow style architecture?
(c) What is control statement? List VHDL control statements.

5 (a) Write a VHDL description for 4:1 multiplexer by using structure model.
(b) Write VHDL description for 4 bit comparator.

6 (a) Design and describe VHDL code for a 8 to 3 priority encoder by using data flow model.
(b) Write VHDL code for half sub-tractor circuit.

7 (a) Write a behavioral description for D flip-flop.

(b) Write a VHDL description for 4 bit binary up counter using an integer signal.

8 (a) Write VHDL description of an 88 asynchronous RAM with separate data inputs and outputs.
(b) Draw and explain the timing diagram for static RAMS.

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