Model Examination Digital Logic Circuits Sub code: EE 46 Sem : IV A Timing: 3 hrs Part A 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

State Demorgans theorem Give few applications of Multiplexer State the disadvantage of SR flip flop What is race around condition? What is flow table table? Differentiate Moore and Mealey model. Define the term hazard. List out the characteristics of TTL circuit. What is HDL? Write a HDL coding for half adder. Part B 11. a)Prove the following using Demorgans theorem AB+CD = AB .CD and (A+B) (C+D) = A+B +C+D b)List out the basic rules that used in Boolean algebra. c)Convert (A+B) (A+C)(B+C) into standard POS form. OR 12. a)Minimize the four variable logic function using Kmap f(A,B,C,D) = 7(0,1,2,3,5,7,9,11,14) b)Explain with the neat circuit diagram the operation of look ahead carry adder 13. a)Design a 3bit synchronous counter using JK flilflop b)Design a 5bit shift register. OR 14. a)Draw an asynchronous decade counter and explain its operation drawing neat waveforms. b)Explain universal shift register 15. Design an asynchronous circuit using JK flip flop that will output only the first pulse received and will ignore any other pulses OR 16. Discuss in detail the various problems seen in asynchronous sequential circuit. 17. a) Draw the block diagram of a PLA device and briefly explain each block. b)Implement binary to excess 3 code converter using ROM. OR 18. a)Draw a CMOS NAND gate and explain its operation . What are the characteristics of CMOS? b)Draw a tristate TTL gate and explain its operation. 19. Write a VHDL code for 8 bit parallel adder / subtractor using structural approach 20. a)Write a VHDL code for 4 bit counter using behavioral model b)Write a VHDL code for 4 to 1 MUX (4) Date: 19.04.11 Year :II Marks : 100

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