RTDSP ASSIGNMENT- VHDL CODE

Dataflow Modelling

1. Write VHDL code for BCD to 7 Segment Converter using WITH SELECTStatement in
dataflow modeling.

VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity seg7_driver is
port(
bcd : in STD_LOGIC_VECTOR(3 downto 0);
seg7 : out STD_LOGIC_VECTOR(6 downto 0)
);
end seg7_driver;

architecture seg7_driver_arc of seg7_driver is

begin

with bcd select

seg7 <= "0000001" when "0000",
"1001111" when "0001",
"0010010" when "0010",
"0000110" when "0011",
"1001100" when "0100",
"0100100" when "0101",
"1100000" when "0110",
"0001111" when "0111",
"0000000" when "1000",
"0001100" when "1001",
"1111111" when others;

end seg7_driver_arc;

2. Write VHDL code for Full-Subtractor in dataflow modeling.

VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SUBTRACTOR_SOURCE is
Port ( A, B, C : in STD_LOGIC;
H_DIFFERENCE, F_DIFFERENCE, H_BORROW, F_BORROW : out STD_LOGIC);
end SUBTRACTOR_SOURCE;

architecture dataflow of SUBTRACTOR_SOURCE is

Begin
---full subtractor
F_DIFFERENCE <= A xor B xor C;
F_BORROW <= ((not A) and (B or C)) or (B and C);
end dataflow;

Behavioural modelling

1. Write a VHDL program to implement 4 to 2 Encoder in behavioural modelling.

VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity encoder1 is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : out STD_LOGIC_VECTOR(1 downto 0)
);
end encoder1;

architecture bhv of encoder1 is

begin

process(a)
begin
if (a="1000") then
b <= "00";
elsif (a="0100") then
b <= "01";
elsif (a="0010") then
b <= "10";
elsif (a="0001") then
b <= "11";
else
b <= "ZZ";
end if;
end process;

end bhv;

2. Write VHDL code for JK Master Flip Flop in behavioural modelling

VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity JK_FF is
port( J, K, clk, rst : in std_logic;
Q, Qbar : out std_logic);
end JK_FF;

architecture behavioral of JK_FF is

begin
process(clk, rst)
variable qn : std_logic;
begin
if(rst = '1')then
qn := '0';
elsif(clk'event and clk = '1')then
if(J='0' and K='0')then
qn := qn;
elsif(J='0' and K='1')then
qn := '0';
elsif(J='1' and K='0')then
qn := '1';
elsif(J='1' and K='1')then
qn := not qn;
else
null;
end if;
else
null;
end if;
Q <= qn;
Qbar <= not qn;

end process;
end behavioral;