©Cranes Software International Limited, Varsity Division V1.

0 2019-20

Test Type Module Test Test Code Verilog SET 2_2019-

20

Subject Advanced Verilog Duration 2hrs Total Marks 100 Marks

HDL
INSTRUCTIONS: (Please read before answering)
1. Do not write on the question paper. Write / Answer only in the answer sheet provided
2. No additional time will be provided to complete the test
3. Your answer sheet will not be evaluated if the instructions are not followed.
I. Answer in one word (6 x 1 = 6)

1. The number of control lines for a 8 – to – 1 multiplexer is

2. The output of a logic gate is 1 when all its inputs are at logic 0. the gate is either
3. A ring counter consisting of five Flip-Flops will have ______ states
4. -8 is equal to signed binary number
5. How many flip flops are required to construct a decade counter
6. How many Flip-Flops are required for mod–16 counter?

II. Answer the following (5 x 2 = 10)

7. Explain the difference between latch and flip flop with waveform
8. What Is Sensitivity List?
9. In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk?
If yes, Why?
10. What Is the Difference Between ===, == and = in Verilog?
11. What Is the Difference between Wire and Reg with a example?

III.Explain the following ( 8x 4 = 32)

12. Describe the Technique to Divide a Clock by 32 times

13. write a 4 bit Gray codes can and its advantages and disadvantages over binary code
14. Draw a half adder circuit using only 2:1 Mux’s
15. Explain difference between blocking and non blocking statement in verilog with
waveform.
16. Write A Verilog Code for Synchronous And Asynchronous Reset D Flip Flop?
17. Draw a circuit which can detect both +ive and –ive edge at the same time.

18. Given only two xor gates one must function as buffer and another as inverter?
19. Draw the circuit for following line of code

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assign wire1 = (sel==1'b1) ? a : b;

IV Design and write the verilog program for the following (6 x 7 = 42)

20. Write a mealy and more fsm for the sequence detector 0101.
21. Draw a detailed Digital Timing Diagram and circuit for UART protocol showing start
stop & data bits with timing
22. Explain FIFO in detail with Timing waveforms.
23. Explain how to convert binary to bcd by taking an example and write verilog code for the
same.
24. Explain the types of loop statement in verilog with example.
25. Explain the working of CRC with hardware implementation for polynomial divisor as
1+x+ x 2 + x 4 and dividend as 1+x+ x 3 + x 5

V Describe your project with architecture and waveform (1x 10 = 10)

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