Regulation: R13 Code : EC443/31

IV B.Tech I/II Semester Supplementary Examinations – July,2019

DIGITAL DESIGN THROUGH VERILOG
Time: 3 hours (ECE) Max. Marks: 60
SECTION – A
Answer all ten questions 10×1M=10M

1. Write the description of and #3 ɡ (a, b, c)is ____________________.

2. In Verilog, Grounded pins are declared as __________ keyword.

3. Verilog has _________ ternary operator.

a) 1 b) 2 c) 3 d) 4

4. Purpose of wire is _______________.

5. Syntax of wait construct is _______________.

6. The repeat construct is well suited for ____________.

7. The delay assignment can be made conditional on an expression, such a path specification
is an _______________.

8. Purpose of specparam is ______________.

9. Which feature is used to write a custom C code to interact with the internal data structures
of Verilog is called as

a) Module b) Simulator c) Editor d) PLI

10. Which of the following is illegal

a ) 4%-3 b) -4%3 c) 4%3 d) none

SECTION – B
Answer all five questions 5×2M= 10M

11. Consider a function to compute the sum of the squares of the first n natural numbers.

12. Write a Verilog code using disable statement.

13. Write a any simple program using verilog?

14. Define programming language interface?

15. Mention few factors that defines the bit width.

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Regulation:R13 Code :EC443/31

SECTION – C
Answer all four questions 4×5M = 20M

16. Implementation of a 4x1 multiplexer using data flow modelling?

(OR)
17. Where the Switch level modeling is used in VLSI and explain the same with Example?

18. Explain the following

(i) Keywords
(ii) Data types
(iii) Identifiers
(iv) Comments
(v) Strings
(OR)
19. Write a short note on scalars and vectors.

20. Explain in detail about Programming Language Interface (PLI).

(OR)
21. List out the operators in verilog with an example?

22. Design an gate level modelling for five input AND gate?
(OR)
23. Explain in detail about strengths and net types.

SECTION – D

Answer all two questions 2×10M= 20M

24. Design and Write an verilog code for comparator inputs are a1,a0,b1,b0 and output are y1
= a < b, y2 = a > b, y3 = (a=b)? (truth table, k-map, equation, circuit diagram, Verilog
program).
(OR)
25. Prepare a module to convert a set of 8 bits in gray code into an equivalent binary number.

26. Explain in detail about Moore and Mealy models with the block diagram.
(OR)
27. Briefly explain combinational and sequential UDPs in Verilog and write Verilog module
for D latch using UDP

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