Efficient methods for analog

mixed signal verification

Interface handling methods, trade-offs and
guidelines
Lakshmanan Balasubramanian, Bharath
Kumar Poluri, Texas Instruments
Shoeb Siddiqui, IITM
Vijay Kumar Sankaran, Cadence

© Accellera Systems Initiative 1

 Acknowledgement
• Jagdish C Rao, Nikhil Chandrakant Sangani of Texas
Instruments (TI) for their support and motivation
• Badrinarayanan Zanwar, Bhanuprakash R and Michael Womac
of Cadence Design Systems (CDS) for their specific technical
contributions and support of towards the studies of several flavours of
CMs for AMS co-simulation
• Abhijeet Kolpekwar, Chong Chi, Ron Vogelsong, Dan Cline,
Michael Dolan, Andre Baguenier and Vishwajeet Betai of CDS
for their untiring support on AMS co-simulation methodology, technical
discussions, brainstorming and formal tool support
• Kalyan Ram Hampapuram, Aswani Kumar Golla, and
Penchalkumar Gajula of TI for their support on several aspects of
backend physical design flow and tools

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 Objective
• Context: AMS co-simulation
• Explain connect modules / interface elements
• Power managed designs
• Introduce different types of CMs
– Compare
– Implementation intricacies
– Automation requirements
• True supply sensitivity
• Recommendations

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 Motivation: Analog mixed signal
• Increasing analog integration
• Increasing system complexity, flexibility and richness
of functionalities
• Time-to-market pressures & first pass silicon success
• Finding issues later in the product or design cycle is
expensive

Quality product on time in the hands of end user

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 AMS co-simulation: Significance
• Digital (Event driven) and analog (SPICE) simulation
engines running simultaneously, in coherence
• To simulate systems having digital and analog contents
– A misnomer!  Not necessarily digital Vs analog
– Mix of (Digital, Behavioural abstraction) & (analog, transistor
level or device level abstraction)
• Necessary though limited scope
– Synopsys: VCS-Nanosim, VCS-HSIM
– Cadence: NC-Ultrasim, NC-Spectre/APS
• Performed at various levels of accuracy and abstraction
– To realistically trade-off simulation run time Vs accuracy
• AMS co-simulation with only focused functions in TL
• Other functions (including analog) as ABMOD

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 Abstraction levels: Cost Vs Accuracy
Method
 Analog
• Digital
 Behavioural models (BMOD)
– Register Transfer Level • Event  Digital equivalent models
(RTL) driven (VHDL/Verilog)

Simulation run time (Speed ) & Cost

– Gate Level (GL)  with • Faster  Analog models using digital tools
timing annotation  VHDL RN (Real Number), Verilog
wreal
DMS

– Analog macro models

• SPICE
• Verilog A
based
analog • Verilog or VHDL AMS
simulator • SPICE macro models

• Slower
Accuracy

– Transistor Level (TL) – Transistor Level (TL)

• Device level models with detailed
characterisation
• Most accurate
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 Abstraction levels: Cost Vs Accuracy
Method
 Analog
• Digital
 Behavioural models (BMOD)
– Register Transfer Level • Event  Digital equivalent models
(RTL) driven (VHDL/Verilog)

Simulation run time (Speed ) & Cost

– Gate Level (GL)  with • Faster  Analog models using digital tools
timing annotation  VHDL RN (Real Number), Verilog
wreal

– Analog macro models

• SPICE
• Verilog A
based
Conventional AMS analog • Verilog or VHDL AMS
simulator • SPICE macro models

• Slower
Accuracy

– Transistor Level (TL) – Transistor Level (TL)

• Device level models with detailed
characterisation
• Most accurate
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 AMS co-simulation setup
Testbench
Selected Analog
simulated in
IOs transistor level
Analog
Mixed Signal SoC modules
simulated
Connect On-chip Analog
in
Module Oscillators BUS
A2D transistor
Functional
level
111

110

Models
101

100

Connect
011

always
010

ADC
001

000

Module
1 2 3 4 5 6 7 8
8 8 8 8 8 8 8 8

Digital D2A
C1
Toplevel Connect
Module Comparator
A2D Digital
Connect BUS
Power
R1 Module Functional
BiDi Management
Models

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 Connect modules for A(D)MS
CM (IE): To handle signals crossing inconsistent data
types
Multiple disciplines
Co-simulation boundary
Logical and real domains

Continuous, Discrete,
real valued binary valued
Variable Variable
E VDD
E2L-CM L
1
tr tf
0 0
0V

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 Connect modules: Basic function
• Level (Voltage) conversion w.r.t a threshold
– Pre-defined constant
– Pre-defined derived function

Logic Output X 0 X 1

Electrical VHI
Pre-defined
Voltage
VLO Voltage Thresholds
Input Vsupmin

Time

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 Connect module flavours
• Voltage & Current handling
• Impedance handling
– Strength based CM
• Supply awareness
– Static CM
– Dynamic CM
• Inherited CM
• Inherited CM with CPF (Power aware CM)
• Supply sensitive CM

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 Static connect modules
• Level (Voltage) conversion w.r.t a pre-defined
constant threshold

Logic Output X 0 X 1

Electrical VHI
Pre-defined
Voltage
VLO Voltage Thresholds
Input

Time

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 Static CM Implementation
connectmodule E2L (Ain, Dout);
input Ain; electrical Ain; // electrical input
output Dout; \logic Dout; // logic output
// INSTANCE PARAMETERS:
parameter real vsup=3.6 from (0:inf); // nominal supply voltage
parameter real vthi=vsup/1.5 from (-inf:vsup); // upper input threshold
parameter real vtlo=vthi/2 from (-inf:vthi); // lower threshold
parameter real vtol=vsup/100 from (0:(vthi-vtlo)/4]; // voltage tolerance
…
// LOCAL VARIABLES:
reg Dreg; // output register
…
initial begin
…
end
…
endmodule

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 Static CM
Multiple voltage & power domain
L2E

E2L

EL
Analog
L2E (Electrical / TL)
E2L
Digital
EL BD
RTL /
GL + L2R
SDF
R2L

RL BD Analog
(Real Numbered
L2R BMOD)
R2L

RL BD

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 PM handling with Static CM
• Identify all the CM instances after compilation and
elaboration
• Classify CM instances among the different voltage
domains
• Assign the variable vsup for each CM instance to constant
value
defparam testbench.duv.a_3v_E2L.vsup=3.0;
defparam testbench.duv.b_1p8v_E2L.vsup=1.8;
• Pursue with simulation; now the setup can comprehend
the difference between different voltage domains even
though in a static manner.

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 Static CM: Summary
• No power domain L2E

E2L
handling EL
Analog
• Manual voltage L2E (Electrical / TL)
domain handling E2L
Digital
– No dynamism RTL /
EL BD

– Fixed supply GL + L2R

SDF
voltage levels per R2L

simulation run RL BD Analog

(Real Numbered
L2R BMOD)
R2L

RL BD

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 Dynamic CM
• Very critical with multiple voltage supplies & levels
1.3 V
Supply
0V

1
D2A input
0 D2A output
doesn’t track
1.4 V supply dynamics
D2A output
Static CM D2A output
0V tracks supply
dynamics
1.3 V
D2A output
Dynamic CM
0V

t0 t1 t2 t

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 Supply inherited connect modules
• Inherits the top-level power net  Uses the voltage
value for conversion (in real time)
• Definition (Global!) in CM overrides physical supply
connectivity
VDD

E E2L - Inh L

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 Supply inh. CM Implementation
connectmodule E2L_inhconn (Ain, Dout); …
input Ain; electrical Ain; // electrical // LOCAL VARIABLES:
input …
output Dout; \logic Dout; // logic real Vds; // supply voltage
output real Vas; // input voltage
// Inherited vdd! and vss! initial begin
electrical …
(* integer inh_conn_prop_name="vdd"; end
integer ...
inh_conn_def_value="cds_globals.\\vdd! "; *) \vdd!
; analog begin
electrical Vds = V(\vdd! ,\vss! );
(* integer inh_conn_prop_name="vss"; Vas = V(Ain,\vss! );
integer …
inh_conn_def_value="cds_globals.\\vss! "; *) \vss! ; end
// INSTANCE PARAMETERS: endmodule
parameter real vsup_min=0.5 from (0:inf); // min
supply for normal operation
// scaled input/output levels/thresholds (0 maps to
Vref, 1 maps to vdd-vss):

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Supply inherited connect modules
Multiple voltage & power domain

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 PM handling with supply inh. CM
• Identify all voltage domains
• Create unique CM definition per domain
– Supply node reference for different domains
– Defining a unique logic discipline (Ex. logicavdd & logicdvdd)

electrical
(* integer inh_conn_prop_name="vdd";
integer inh_conn_def_value=“testbench.avdd"; *) \avdd! ;
electrical
(* integer inh_conn_prop_name="vss";
integer inh_conn_def_value=“testbench.avss"; *) \avss! ;
electrical
(* integer inh_conn_prop_name="vdd";
integer inh_conn_def_value=“testbench.dvdd"; *) \vdd! ;
electrical
(* integer inh_conn_prop_name="vss";
integer inh_conn_def_value=“testbench.dvss"; *) \vss! ;

• Classify the different cells, cell instances, instance terminals and nets into
logic domains
– Use the backend physical design tool
• Pursue with compilation, elaboration and simulation

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 Supply inherited CM: Summary
• No power domain
handling
• Semi-automated voltage
domain handling
– Discipline definitions
• Logical: Multiple supply
domains
– Superficial (not through
physical supply
connectivity) supply
dependence definition
– Dynamism supported
• Power-up/down (ramp) &
mode transitions

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 Supply inherited CM with C/UPF
• Voltage conversion based upon whether that
particular power domain is active or not
• Definition (Global!) in C/UPF overrides physical
supply connectivity
VDD1 Inactive
VDD2

E2L - Inh

E L
E2L - Inh x

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 Supply Inherited CM with C/UPF
Summary
• Power domain handling
– CPF / UPF
• Semi-automated voltage
domain handling
– Discipline definitions
• Logical: Multiple supply
domains
– Superficial (not through
physical supply
connectivity) supply
dependence definition
– Dynamism supported
• Power-up/down (ramp) &
mode transitions

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 True supply sensitive CM
• References the Logic Ordinary Module (LOM) of the
port it is connected to  Uses the SS info of the port

VDD

(*VDD*)

E E2L - SS L

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 SS CM implementation
connectmodule E2L_ss (Ain, Dout);
input Ain; electrical Ain; // electrical input
output Dout; \logic Dout; // logic output
// Supply Sensitivity attributes
electrical (* integer supplySensitivity = "cds_globals.\\vdd! " ; *) \vdd! ;
electrical (* integer groundSensitivity = "cds_globals.\\vss! " ; *) \vss! ;
// INSTANCE PARAMETERS:
…
initial begin
…
end
...
analog begin
…
end
endmodule

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 Requirements on design elements
• SS information in all design elements
– Definitions of Standard cells, IOs and ABMODs

input VCC;
input VDD;
input (* integer supplySensitivity = "VCC" ; integer groundSensitivity = "VSS" ; *) a_3p0v;
input (* integer supplySensitivity = "VDD" ; integer groundSensitivity = "VSS" ; *) a_3p0v;

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 True supply sensitive CM
Multiple voltage & power domain
• Power domain L2E

handling E2L

– CPF / UPF EL
Analog
• Fully automated Digital L2E (Electrical / TL)
voltage domain RTL + E2L
handling CPF /
EL BD
– SS constructs in GL +
models & RTL SDF L2R Analog
+ SS (Real Numbered
– Dynamism constr R2L
supported BMOD)
ucts RL BD
+ CPF (not
• Power-up/down
(ramp) & mode L2R supported)
transitions + SDF (not
R2L
supported)
RL BD + SS constructs

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 SS CM: DMS Vs AMS compatibility
Homogeneous SS
• Electrical ABMODs (VAMS)
• No DMS & always need co-simulation over head
VDD (E) VDD (E)

E
E L L
L

SS: E
Works: No

VDD (E)
L
L
L

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 SS CM: DMS Vs AMS compatibility

• RN ABMODs with supply as real

VDD (R) VDD (R)

R
L L L
(BMOD)
R

VDD (R)
L
L
L

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 SS CM: DMS Vs AMS compatibility
Heterogeneous SS
• CM insertion on the supply path
• Can also be handled through discipline resolution
algorithm & CM optimisation
VDD (E) VDD (R)

R
E SS: E
L L
Works: No
R

VDD (R)
L
SS: E L
Works: No
L
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 SS CM: Limitations
1. Logical power awareness
• PA GLS
– Requires logical operation on supply
– Supply path CM insertion
• Sensitive on itself!  Difficult to handle
• Especially on real supply
– Hypothesis: If supported  Number of CM blows-up
• Performance / Run time impact
• Is it really needed?
– SS on WELL/BODY & PA on supply, vice-versa
– No PA in AMS
• SS CM handles 1st stage PA
• RTL/GLS/DMS regressions to be PA for coverage

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 SS CM: Limitations
2. Out of module references
• OOMR
– Assertions for metric driven verification (MDV)
– Avoid waveform analysis  Improves efficiency
– CM insertion  What is the sensitivity?
• Use access functions / built-in tasks
CDS_GET_ANALOG_VALUE
$SNPS_GET_VOLT, $SNPS_GET_PORT_CURRENT
– Avoids CM insertion for OOMR and hence handling SS

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 SS CM: Limitations
3. Performance impact
• Heterogeneity
– Number of CMs can blow-up
– Algorithmic or SS type handling
• GL-AMS
– Number of CMs can blow-up due to fan-out nodes

– Algorithmic improvement
• CM optimisation on signal path
• Merge supply at least for E2L

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 SS CM: Superiority
• No verification side bottleneck in setup
• Power and SS intent
– Available at design

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 Comparison & Recommendations
S. Supply sensitive CM Power aware
Requirements Static CM Supply inherited CM
No (CPF/UPF)
Dynamic with Dynamic with
1 Power awareness Inherently not supported. Dynamic with global.
actual. global.
Multiple voltage and Static support using custom Dynamic, not Dynamic & Dynamic, not
2
power domains setup requiring high effort. connectivity aware. connectivity aware. connectivity aware.
Low. Initial effort None. Reuses
Negligible for designs with High in defining
spread across each existing PA RTL
3 Setup effort single supply. High for power disciplines. Custom
design element. simulation flow
managed (PM) designs. automation possible.
setup.
Performance issue CPF may be
GL simulation
4 None. None. due to CM blow-up. stripped which has
concerns
SS information.
High effort. Custom Very high effort, if
Migration of legacy Low effort. Same as new Moderate effort.
5 automation no CPF/UPF
designs design. Same as new design.
possible. available.
PM designs at PM design at early PM designs with
Recommended design mature stage. stage. Designs CPF/UPF, with no GL
6 Non-PM designs.
flavours & stage Designs not having SS having SS AMS requirement.
information. information.
Sandwitch AMS Additional discipline No additional effort. Not evaluated.
7 No additional effort.
configuration handling required.
Heterogeneity & GL-AMS simulation
Improvements String parameter support for
8 None. Hierarchical CM support.
needed vsup.
optimisation.

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 Conclusions
• AMS co-simulation is in-escapable for AMS SoC
• CM (IE) is inherent to any co-simulation for
discipline/domain crossings
• Flavours of CM evolved
– Static, Supply inherited, SI with C/UPF & Supply sensitive
– Practical tips, and automation needs identified
• Power managed designs are common
– SS CM is superior on intent transfer & reducing verification
setup bottleneck
– Limitations exist: Collaboration underway for solutions
• Comparison and recommendations provided

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 Questions

Thanks for your interest, attention,

and time

© Accellera Systems Initiative 38