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Vector based dead-time compensation for a three-level T-type converter

Conference Paper  in  IEEE Transactions on Industry Applications · March 2015

DOI: 10.1109/APEC.2015.7104551

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 Vector based Dead-Time Compensation for a
Three-level T-Type Converter

Xiong Li, Serkan Dusmez, Bilal Akin, and Kaushik Rajashekara

Erik Jonsson School of Engineering and Computer Science
the University of Texas at Dallas
Richardson, Texas 75080
Email: li.xiong@utdallas.edu

Abstract—This paper proposes a new vector based dead time

compensation method for a three-level T-type converter. The
origin of dead time voltage error is analyzed in detail under
different switch commutation processes and load conditions.
Based on the dead time voltage error for each phase, an error
voltage vector is defined to indicate the effect of dead time
on the reference voltage vector from vector synthesis point of
view. To cancel the dead time error voltage vector, the reference
voltage vector is adjusted accordingly based on load current
directions. The operation of the proposed dead time compensation
method can be extended to over modulation region also. The
effectiveness and the advantages of the proposed vector based
dead time compensation method are verified by both simulation
and experimental results. Fig. 1. Power circuit diagram of a three-level T-type converter

TABLE I. SWITCHING TABLE

I. I NTRODUCTION
T-type converters are becoming popular for low voltage
applications such as automotive and photovoltaic converters,
to achieve higher energy conversion efficiency at lower cost
[1], [2]. The power circuit diagram of a T-type converter
is shown in Fig. 1. To prevent short circuit of the dc link
capacitors, a dead time is usually inserted in the gating signals
of the power switches of each leg. This dead time is of
relatively short duration in comparison to the period of the
low-frequency modulating waveform. However, its cumulative
effect over multiple cycles of the carrier waveform increases
the harmonic distortion and reduces the effective value of the
synthesized voltage [3]. These effects are more pronounced at
high switching frequencies. The effects of dead time in two-
level voltage-source converters have been comprehensively
studied, and different solutions have been proposed [4]–[7].
However, majority of the proposed dead time compensation
schemes in the literature operate under limited modulation
index to avoid the saturation of the gating pulses. In [7], a
concept of dead time compensation with variable switching
frequency is proposed. By decreasing switching frequency,
effective gating pulse width can be extended. Nevertheless,
variable switching frequency control raises challenges on the
design of the EMI filters, and introduces additional current
harmonics. Few papers [8], [9] discussed the dead time com-
pensation for three-level voltage source converters. Still, the
proposed strategies encounter the issues mentioned above. In
this paper, a new vector based dead time compensation scheme
is proposed for three-level T-type converters. An error voltage
vector is introduced to indicate the effect of the dead time
on the reference voltage vector. The reference voltage vector
is adjusted accordingly to compensate this dead time effect.
With the proposed scheme, the modulation index can also be
Switching state S1 S2 S3 S4 Pole voltage
P 1 0 0 1 Vdc
Vdc
O 0 0 1 1 2
N 0 1 1 0 0
extended through operating the converter at over modulation
region. More details are given in the following part of the
paper.
II. ANALYSIS OF EFFECT OF DEAD TIME
For a three-level T-type converter, each phase can generate
three voltage levels. The switching table of a three-level T-
type converter is presented in Table I. Three switching states
P, O and N are defined to indicate the three voltage levels.
The switching commutations of a three-level T-type converter
should be considered carefully to modulate the output voltages,
while to avoid dc bus short circuit. To prevent short circuit
of the dc bus, a dead time is usually inserted in the gating
signals of the power switches of each leg. The inclusion of
the dead time may cause a voltage error depending on the
directions of the load currents and switching transitions. To
explain the effect in detail, the commutation processes from
switching state P to O of one leg under different load currents
are discussed as following. The circuit configurations for the
commutation processes are displayed in Fig. 2, while the
switching patterns are presented in Fig. 3(a). When the load
current is positive, the switching state is O, which is the desired
one, during the dead time period. Under this condition, the
inclusion of the dead time doesnt introduce any voltage errors.
However, the switching state is P during the dead time period
 TABLE II. COMMUTATION PROCESS AND VOLTAGE ERROR

Voltage error k
Switching transition Switching sequence
ix > 0 ix < 0 ix > 0 ix < 0
N →O Sx2 = 0 → Sx4 = 1 −4v 0 −1 0
O→N Sx2 = 0 → Sx4 = 1 0 4v 0 1
O→P Sx2 = 0 → Sx4 = 1 −4v 0 −1 0
P →O Sx2 = 0 → Sx4 = 1 0 4v 0 1

Fig. 2. Commutation processes from P to O. (a) when the load current is

positive. (b) when the load current is negative.

Fig. 3. (a) Switching pattern when the switching state commutes from P to
O. (b) voltage error in two-level approximation compensation method.

when the load current is negative. Because of this, a voltage

error is generated. Other switching state commutations under
different load conditions can be analyzed in a similar way,
which are summarized in Table II. From Table II, it can be seen
that the profile of voltage error caused by the dead time for a
three-level converter is similar to that for a two-level inverter.
The voltage error caused by the dead time effect is load current
and switching transition dependent. A positive voltage error
occurs at the falling edge transitions when the load current is
negative, while a negative voltage error is generated at the
rising edge transition when the load current is positive. A
general formula is defined to calculate the dead time voltage
error with two-level approximation compensation method, the
profile of which is presented in Fig. 3(b), as shown in Eq. (1).
Vdc
4v = k × 4d ×
2
where, 4d = Ttdb sw
, tdb is the inserted dead time; Tsw is the
switching period; Vdc is the dc bus voltage; k is a coefficient.
From Eq. (1), it can be known that the voltage error is related
with half dc link voltage, but not whole dc link voltage as
the case for two-level inverters. Thus, the dead time effect for
three-level converters is smaller as compared with that for two-
level converters. It is also worth mentioning that the Eq. (1) can
be utilized to calculate the voltage error only if the switching
transitions occur in between adjacent switching states. Please
note that the voltage error caused by switching transients can
be grouped into 4v, which will not affect the implementation
of the proposed dead time compensation method.
Fig. 4. (a) First sextant of the space vector diagram of the three-level T-type
converter. (b) switching sequence of region 1.
III. VECTOR BASED DEAD TIME COMPENSATION
Symmetric space vector modulation (SSVM) scheme is
widely used to modulate the output voltage while to balance
the neutral point voltage of three level inverters. With the
SSVM, each sextant of the space vector diagram is divided
into four regions i. e. as shown in Fig. 4(a). In order to reduce
the switching frequencies of the devices, regions 2 and 4 are
(1) now split into 2L, 2H, 4L, and 4H. The best vector switching
sequences in the first sextant are given in Table II of [10].
All of these sequences require the same number of switching
steps. The switching sequence in region 1 is presented in Fig.
4(b). From Fig. 4(b), it can be seen that there are one turn-on
transition and one turn-off transition for each phase in each
switching cycle. With reference to Table II, under different
load current directions, each phase would generate a dead
time voltage error. A dead time error voltage vector is defined
here to indicate the effect of three phase dead time voltage
errors on the reference voltage vector. For example, the effect
is demonstrated in Fig. 5 when phase A and B currents are
positive while the phase C current is negative. As shown in
Fig. 5, the voltage error along phase A and B is −4v, and the
Fig. 5. Dead time error voltage vector when ia > 0, ib > 0, ic < 0.

TABLE III. ADJUSTMENT OF REFERENCE VOLTAGE VECTOR Fig. 6. Dead time error voltage vector under different load current directions
a)ia > 0, ib > 0, ic < 0.b)ia > 0, ib < 0, ic > 0.c)ia > 0, ib < 0, ic <
ia ib ic Reference voltage adjustment 0; d)ia < 0, ib > 0, ic > 0; e)ia < 0, ib > 0, ic < 0; f )ia < 0, ib <
0, ic > 0.
Vref 2α = Vref α + 4d
>0 >0 <0
Vref 2β = Vref β + 24d
√
3

Vref 2α = Vref α + 4d
>0 <0 >0
Vref 2β = Vref β − 24d
√
3
n
Vref 2α = Vref α + 2 4 d
>0 <0 <0
nVref 2β = Vref β
Vref 2α = Vref α − 2 4 d
<0 >0 >0
Vref 2β = Vref β
Vref 2α = Vref α − 4d
<0 >0 <0
Vref 2β = Vref β + 24d
√
3

Vref 2α = Vref α − 4d
<0 <0 >0
Vref 2β = Vref β − 24d
√
3

one along phase C is +4v. Overall, the vector presentation of
the dead time voltage errors is illustrated with red arrow line,
the magnitude of which is 2 4 v. Analogously, the dead time
error voltage vector under different load current directions is
displayed in Fig. 6(a)-(f).
Fig. 7. Adjusting of the reference voltage vector for dead time compensation.
adjustments of the reference voltage vector under other load
current conditions are summarized in Table III. The effect of
the error voltage vector for one line cycle is shown in Fig. 8.

To compensate for the voltage errors caused by the in-

clusion of dead time between switches, the reference voltage
vector should be adjusted accordingly. As shown in Fig. 7,
the commanded reference voltage vector is Vref , which is dis-
played with solid blue arrow line. Without any compensation,
the actual reference voltage vector would become Vref 1 due to
the effect of error voltage vector as shown with solid red arrow
line. In order to cancel out the effect of dead time, the reference
voltage vector should be adjusted to Vref 2 to counterpart the
error voltage vector generated by the dead time effect. For the
case shown in Fig. 7, the adjustment of the reference voltage
vector could be realized with a simple approach as presented
in Eq. (2).

Vref 2α = Vref α + 2 × 4d
(2)
Vref 2β = Vref β
where Vref α and Vref β are the projections of the reference
vector; Vref 2α and Vref 2β are the projections of the adjusted
reference voltage vector along alpha and beta axes. The
IV. DEAD TIME COMPENSATION IN DEEP MODULATION
REGION
There are some challenges on the dead time compensation
in the deep modulation regions with conventional pulse width
based approaches as discussed in [8]. The basic ideas behind
the pulse width based dead time compensation is to directly
extend or shorten the corresponding pulses according to the
load current directions and switching state transitions. The
pulse width based approach can operate well in the most
operation regions. However, the compensation would become
ineffective when the extended pulse widths become saturate.
An example is given here to help explain the issue. As shown
in Fig. 9, one switching sequence in the deep modulation
region is presented. Assuming that for the case shown in Fig.
9, the phase A current is positive. Then, a negative voltage
error would be generated. To compensate for the voltage error,
the gating pulse width of the corresponding phase should be
 Fig. 11. Generalized switching pattern of a N-level converter.

Fig. 8. Effect of dead time on the reference voltage vector under unity power
factor loading.

Fig. 12. Commutation process of a four-level diode clamped converter when

the load current is positive.

extended. With the pulse width extension, the pulse width of

Fig. 9. Switching pattern without dead time compensation in deep modulation
region.
S1 can be recalculated as in Eq. (3).
dax = da + 4d (3)
According to Fig. 9, the pulse width of S1 becomes saturate
after compensation, which means the effect of the dead time
cannot be fully compensated.
To deal with the pulse width saturation issue, a variable
switching frequency approach is proposed in [7]. The basic
idea there is to extend the pulse width over one switching
period by reducing the switching frequency thus to avoid pulse
width saturation. The method in [7] can be utilized to further
extend the pulse widths in deep modulation regions, while
there are some side effects with it. On one hand, the varying of
the switching frequency challenges the design of EMI filters
and passive filtering components. One the other hand, the
reduction on the switching frequency would bring more current
harmonics. Nevertheless, the pulse width saturation issue could
be smoothly solved with the vector based compensation ap-
proach, by pushing the operation into over modulation regions.
In Fig. 10, the dead time compensation in over modulation
regions is presented. Same as the dead time compensation
in linear modulation regions, the dead time voltage vector
can be determined according to the load current directions.
The reference voltage vector can be adjusted accordingly. The
reference voltage vector in the over modulation regions can
be synthesized with the scheme as presented in [11]. Because
of the operations in the over modulation regions, there could
be existing more harmonics compared with that in linear
modulation regions, while the switching frequency can be held
as constant.

V. GENERALIZED FORM FOR MULTILEVEL CONVERTERS

Fig. 10. Dead time compensation in over modulation region. The proposed vector based dead time compensation strat-
egy can be applied to multilevel converter with any voltage
levels. With nearest three vectors (N3V) based SVPWM, the
switching state of each phase toggles between two adjacent
switching states. The generalized switching pattern can be
presented as in Fig. 11. There are one rising edge and one
falling in each switching sequence of each switching period
for each phase, which is the same as that for a three-level
converter. A voltage error caused by dead time could be
generated depending on the direction of the load current. More
specifically, a positive voltage error would be generated at the
falling edge if the load current is negative, while a negative
voltage error could be created at the rising edge if the load
current is negative. A generalized form to calculate the voltage
error is shown as in Eq. (4).
Vdc
4v = 4d (4)
N −1
where N is the number of voltage level; 4d is the dead time
duty ratio; Vdc is the dc link voltage. To support the analysis,
one example is given here. In Fig. 12, the commutation process
of a four-level diode clamped converter is shown. In Fig. 12(a),
the output is 0. To change the output voltage from 0 to Vdc /3,
the switch S6 should be turned off while the switch S3 should
be turned on. To avoid short circuit condition of capacitor C3 ,
a dead time is inserted between the turn off instant of S6 and
turn on instant of S3 . During the dead time period, as shown in
Fig. 12(b), the output voltage is 0, while the expected output
voltage is Vdc /3. Thus a voltage error of Vdc /3 is generated
here. Average the voltage error within one switching period,
the effective voltage can be calculated according to Eq. (4).
For multilevel converters with other number of voltage levels,
the voltage error can be derived in an analogous way. Once
the dead time voltage error of each phase is calculated, the
error voltage vector can be obtained, and the reference voltage
vector can be adjusted accordingly for compensation.
VI. SIMULATION AND EXPERIMENTAL RESULTS
Simulation and experimental results are conducted to verify
the effectiveness and advantages of the proposed vector based
dead time compensation strategy. The dc link voltage is 400V,
and the output of the converter is connected with a resistive
load. A LC filter with a bandwidth of 2 kHZ is utilized to
smooth the load currents. The switching frequency of the
converter is 10 kHz, while the fundamental frequency is 60Hz.
The relationship between the load current THD and dead time,
when modulation index ma is 1, is sketched in Fig. 13, from
which it can be known that a larger dead time could cause
a higher current distortion. In Fig. 14, the simulation results
of line voltage and line current with different dead time are
presented. From Fig. 14, it can be clearly seen that higher
voltage loss occurs at larger dead time. The voltage reference
signals and three phase line currents with/without dead time
compensation are shown in Fig. 15. The frequency spectrums
of load current under different conditions are presented in
Fig. 16. From the comparison of the frequency spectrums, it
could be known that both the voltage magnitude and quality
can be compensated with the dead time compensation. The
experimental results of line voltage and current are shown in
Fig. 17. From the results, it can be seen that the line current
is less distorted after dead time compensation.
Fig. 13. Relationship between current THD and dead time [ma = 1].
VII. C ONCLUSION
This paper proposes a new vector based dead time com-
pensation method for a three-level T-type converter. Based on
the dead time voltage error along each single phase, an error
voltage vector is defined to indicate the effect of dead time
on the reference voltage vector from a synthesized point of
view. To counterpart the dead time error voltage vector, the
reference voltage vector is adjusted accordingly based on load
current directions. With the proposed vector based dead time
compensation strategy, the pulse width saturation region can
be extended by pushing the operation into over modulation
regions. The effectiveness and the advantages of the proposed
vector based dead time compensation method are verified by
the both simulation and experimental results.
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