A Seven-Level Boost Inverter for Medium Power
PV Applications
Omar Abdel-Rahim*, **, Senior Member, IEEE and Haoyu Wang*, Senior Member, IEEE
*
School of Information Science and Technology, ShanghaiTech University, Shanghai, China
** APEARC, Faculty of Engineering, Aswan University, Aswan, Egypt
wanghy.shanghaitech@gmail.com
Abstract—Conventional multilevel inverters typically
utilize high component count and cannot step up the
input voltage. This paper presents an improved
multilevel boost-type inverter with low component
count. The proposed inverter is able to generate a seven-
level ac output voltage (0, 0.5Vdc, Vdc, 1.5Vdc, -0.5Vdc, -Vdc, -
1.5Vdc), while only eight switches and three capacitors are
employed. The charge pump principle helps to boost the
output voltage to 1.5 times of the input voltage. A level-
shift pulse-width-modulation mechanism is introduced
to drive the switches. The switch pattern is designed to
balance the capacitors’ voltages and to control the
charge/discharge of the filtering capacitor. In order to
verify and validate the proper operation of the
developed circuit configuration, the system is simulated
in MATLAB/Simulink and are experimentally evaluated
using a hardware set-up. Obtained results agree well
with the theoretical analysis. A low total-harmonic-
distortion is achieved with low filter requirement and
the capacitor voltages are well balanced with the level-
shift pulse-width-modulation pattern.
Keywords—Charge pump principle, level-shift pulse-width-
modulation (LS-PWM), multilevel inverters, seven-level.
I. INTRODUCTION
Conventional two level inverters such as H-bridge
inverter are flawed with low reliability, high voltage stress,
and bulky filters [1]-[7]. Therefore, in medium and high
power applications, they are being replaced by multilevel
inverters [8]-[10]. Multilevel inverter generates output
voltage in staircase shape with high power quality and high
conversion efficiency. However, with the increase of voltage
levels, the count of switches, drivers and capacitors increases
dramatically. Moreover, special attention needs to be paid to
the voltage balance of capacitors.
In general, multilevel inverters evolve towards solutions
with reduced components count and balanced capacitor
voltage [11]-[13].
Multilevel inverters can be divided into three categories:
neutral point clamped (NPC) [14]-[17], cascaded H-bridge
[18]-[19] and flying capacitors [20]-[22] inverters.
In grid connected photovoltaic (PV) systems, the terminal
voltage of PV panel is low and varies with the environmental
conditions. Therefore, an intermediate Boost converter is
typically required. This Boost converter degrades the system
power density and conversion efficiency. Alternatively,
charge pump technique can also boost the voltage without
the need for inductors [23]. The charge pump circuit steps up
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c
b
a
S2
S8
C1
S5 S1
VDC
ia
A
n Co
C2
ib
S6 S3
ic
S7 S4
Fig. 1. General schematic of proposed seven-level boost inverter.
the voltage using switch capacitor principle. The capacitors
are charged in parallel while discharged in series, or vice
versa [24].
Different seven-level inverters have been presented in
literature. In [25], a seven-level boost converter is presented
to boost the output voltage to 1.5 times of input voltage.
However, it utilizes 10-switches. Large number of switching
devices may lead to increased system cost and degraded
efficiency.
In [26] authors has presented unique single-phase seven-
level multilevel inverter for PV applications. Although the
topology can generate seven-level, but it doesn’t have
boosting ability and big number of diodes are utilized.
In [27], a seven-level multilevel inverter is developed to
generate the required level with reduced switching device
count. Seven switches and two diodes are employed.
However, the topology is not able to boost the input voltage.
In this paper, a new seven-level converter is proposed.
The general schematic of the developed structure is plotted in
Fig. 1. As shown, single phase version requires 8 switches
and one flying capacitor to generate 7 level output voltage
with amplitude higher than input voltage, while three-phase
version requires 24 switches and three flying capacitors.
The proposed converter is able to boost the input voltage
by a factor of 1.5 using charge-pump principle. For
generating the required pulses for the switches, level-shift
pulse-width-modulation technique is applied.
3316

S2
S8
C1
S5 S1
VDC
LF
n Co A
C2 Vo
S6 S3
B
VG
S7 S4
B
Fig. 2. Schematic of the proposed novel seven-level boost
inverter.
II. TOPOLOGY DESCRIPTION AND OPERATION PRINCIPLES
The single-phase schematic of the proposed seven-level
boost inverter is depicted in Fig. 2. VDC is the input voltage,
Vo is the output voltage, C1 and C2 are the input capacitors
with n serving the neutral point, and Co is the flying
capacitor. C1 is equals to C2, which means they splits the
input voltage evenly. As shown, the developed topology has
only 8 switches, 2 of them do not require anti parallel diode.
This means they could be implemented with IGBT or with
series connection of MOSFET and diode. Switching devices
have different voltage stresses, as summarized in Table I. S5
and S6 have their voltage stresses compared to the other six
switches, while S7 and S8 have to withstand twice of the
input voltage. Eight valid switching states are used to
generate the seven level profile. All valid switching states
are mentioned in Table. II. The maximum number of ON
state switches is three. Indeed, in most of the cases, only two
switches are ON. This helps to reduce the semiconductor
conduction loss. The operation modes are depicted in Fig. 3.
The circuit operation can be divided into 8 modes.
Mode 1, the inverter generates an output voltage equals
Vdc/2 [see Fig. 3 (a)]. S1, S2 and S4 are ON, and the other
switches are OFF. C1 and C2 are charged from the dc source
with a matched voltage, Vdc/2. Co is charged from the input
voltage source and its steady-state voltage equals Vdc.
Output positive terminal (A) is connected to the positive
terminal of C1 and output negative terminal (B) is always
connected to the neutral point of the capacitors.
Mode 2, the inverter generates an output voltage equals
to 0 [see Fig. 3 (b)], S1 and S5 are ON, and other switches
are OFF. C1 and C2 are charged from the dc source and they
have equal voltage value of Vdc/2. Co is floating. This mode
is a freewheeling stage. Output positive terminal (A) and (B)
are connected to the neutral point of the switched capacitor
Mode 3, the inverter generates an output voltage equals
to Vdc [see Fig. 3 (c)], S1 and S6 are ON, and other switches
are OFF. C1 and C2 are charging from the dc source and
they have equal voltage value of Vdc/2. Co is discharging its
stored energy to the load. Output positive terminal (A) is
connected to the positive terminal of capacitor Co.
Mode 4, the inverter generates an output voltage equals
to 1.5Vdc [see Fig. 3 (d)], S1 and S7 are ON, and other
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TABLE I. VOLTAGE STRESSES OF SWITCHING DEVICES
Switching device Voltage stress
S 1, S 3 VDC
S 2, S 4 1.5VDC
S 5, S 6 VDC
S 7, S 8 2VDC
switches are OFF. C1 and C2 are charged from the dc source
and they have equal voltage value of Vdc/2. Co is now in
series with capacitor C2. Output positive terminal (A) is
connected to the positive terminal of Co.
Mode 5, the inverter generates an output voltage -Vdc/2,
[see Fig. 3 (e)]. S2, S3 and S4 are ON, and other switches are
OFF. C1 and C2 are charged from the dc source and they
have equal voltage value of Vdc/2. Co is charged from the
input voltage and it is steady state value equals Vdc. Output
positive terminal (A) is connected to the negative terminal
of C2.
Mode 6, the inverter generates output voltage equals to 0
[see Fig. 3 (f)], S3 and S6 are ON, and other switches are
OFF. C1 and C2 are charged from the dc source and they
have equal voltage value of Vdc/2. Co is floating. This mode
is a freewheeling stage. Output terminals (A) and (B) are
connected to the neutral point of the switched capacitor.
Mode 7, the inverter generates an output voltage equals
to -Vdc, [see Fig. 3 (g)], S3 and S5 are ON, and other switches
are OFF. C1 and C2 are charged from the dc source and they
have equal voltage value of Vdc/2. Co is discharging its
stored energy to the load. Output positive terminal (A) is
connected to the negative terminal of Co.
Mode 8, the inverter generates an output voltage equals
to -1.5Vdc [see Fig. 3 (h)], S3 and S8 are ON, and other
switches are OFF. C1 and C2 are charged from the dc source
and they have equal voltage value of Vdc/2. Co is now in
series with C2. Output positive terminal (A) is connected to
the negative terminal of capacitor Co.
III. LEVEL SHIFT PULSE WIDTH MODULATION
A level-shift pulse-width-modulation (LS-PWM)
mechanism is introduced to modulate the proposed 7-level
inverter. According to [28]-[29], n-level inverter requires (n-
1) carrier waveforms and a reference signal. As the
proposed topology has seven levels, six carriers are
employed, as depicted in Fig. 4. The switching pattern is
determined by comparing the carrier signals with sinusoidal
reference signal. The six carriers are symmetrical with
identical amplitude, phase shift, and switching frequency.
The modulation procedure represents six different sectors.
In Sector 1, the reference signal is compared with carrier
signal e4 and generates an output voltage from zero to –
0.5Vdc.
In Sector 2, reference signal is compared with carrier
signal e5 and generates an output voltage from -0.5Vdc to –
Vdc.
In Sector 3, reference signal is compared with carrier
signal e6 and generates an output voltage from –Vdc to –
1.5Vdc. Due to the symmetrical operation, the positive half
cycle is illustrated with the same procedure.
 S8 S2 S8 S2
C1 C1
S5 S1 VDC S5 S1
VDC LF n LF
n A A
Co Co
S6 S3 S6 S3
C2 Vo VG C2
Vo VG
B S7 B S7 S4
S4
B B
(a) (b)

S8 S2 S8 S2
C1 C1
S5 S1 VDC S5 S1
VDC LF LF
n n A
A
Co Co
S6 S3 S6 S3
C2 Vo C2 Vo
VG VG
B S7 S4 B S7 S4
B B
(c) (d)

S8 S2 S8 S2
C1 C1
S5 S1 VDC S5 S1
VDC LF n LF
n A A
Co Co
S6 S3 S6 S3
C2 C2 Vo
Vo VG VG
B S7 S4 B S7 S4
B B
(e) (f)

S8 S2 S8 S2
C1 C1
S5 S1 VDC S5 S1
VDC LF n LF
n A A
Co Co
S6 S3 S6 S3
C2 C2 Vo
Vo VG VG
B S7 S4 B S7 S4
B B
(g) (h)

Fig. 3. Operation modes of the proposed converter (a) Mode 1, (b) Mode 2, (c) Mode 3, (d) Mode 4, (e) Mode 5, (f) Mode 6, (g) Mode
7, and (h) Mode 8.

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 TABLE II. POSSIBLE SWITCHING STATES OF THE NEW BOOST SEVEN LEVEL INVERTER.
State S1 S2 S3 S4 S5 S6 S7 S8 Output
V0 1 0 0 0 1 0 0 0 0
V1 1 1 0 1 0 0 0 0 Vdc/2
V2 1 0 0 0 0 1 0 0 Vdc
V3 1 0 0 0 0 0 1 0 1.5 Vdc
V4 0 0 1 0 0 1 0 0 0
V5 0 1 1 1 0 0 0 0 - Vdc/2
V6 0 0 1 0 1 0 0 0 - Vdc
V7 0 0 1 0 0 0 0 1 -1.5 Vdc

1 2 3 2 1 4 5 6 5 4 TABLE III. SYSTEM PARAMETERS

1.5EC
e3 Parameter Description Value
EC fs Switching frequency 5 kHz
e2
C 1, C 2 Input capacitors 500 μF
0.5EC ref
e1 Ts Sampling time 25 μs
0
e4 t Co Flying capacitor 5 mF
-EC
e5
-0.5EC TABLE IV. HARDWARE SYSTEM PARAMETERS
e6
-1.5EC Parameter Description Value
IRFP264 Power MOSFET -
1.5Vdc C1=C2 Input capacitors 460 μF

Vdc Ts Sampling time 40 μs

0.5Vdc fs Switching Frequency 5 KHz

Co Flying capacitor 10 mF
0
-0.5Vdc
-Vdc multilevel-inverter. Camera-shot for the hardware set-up is
shown in Fig. 9. Parameter used to build the hardware set-up
-1.5Vdc
is summarized in Table IV. Level-shift PWM is
implemented using DSPACE 1202. Pulses applied to the
power switches are captured in Figs 10 and 11. S1 and S4 are
Fig. 4. The scheme of adopted level-shift pulse-width operating at fundamental frequency, while other switches
modulation. are working at high switching frequency. The measured
output voltage and voltages of C1, and C2 are captured in
Fig. 12

IV. RESULTS AND DISCUSSIONS V. CONCLUSIONS AND FUTURE WORK

In order to validate the proposed concept, a simulation
model is built in MATLAB/Simulink and then A hardware
prototype is implemented inside the laboratory. Parameters
used in simulation and real time implementations are
summarized in Table III.
In Fig. 5, the system is simulated with resistive load, no
output filter is added. Output voltage and output current are
staircase with seven level (0, 0.5Vdc, Vdc, 1.5Vdc, -0.5Vdc, -
Vdc, -1.5Vdc). As shown, C1 and C2 have their voltages
matched to 0.5Vdc, while Co has its voltage equals to Vdc.
The THD of the output current in this case of study is
illustrated in Fig. 6 and it is found to be 47%.
Fig. 7 shows the simulation results with R_L load. Load
current becomes smoother due to inductive load. The total
harmonic distortion is reduced to 22% as shown in Fig. 8.
Experimental prototype has been built in laboratory to
validate the operation of the proposed seven-level
A novel seven-level inverter with boosting ability is
developed in this paper. The proposed inverter is able to
generate a seven-level output voltage with boosting ratio of
1.5. It is constructed from eight-switches, two of them (S1
and S3) operates at fundamental frequency. Two switches
(S2 and S4) does not require anti-parallel diode, where they
could be implemented using IGBT or series connection of
MOSFET and diode.
In order to generate switching signals for the inverter
switches, level-shift PWM technique is employed, where
six-carriers are used to generate the required number of
voltage levels.
Level-shift PWM is designed to keep capacitor voltage
balanced and control the voltage of the neutral point. The
system was simulated with MATLAB/Simulink and
hardware set-up has been built in the laboratory. Obtained
results agreed well with the theory analysis.

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 Vo(V)
400
Vin(V)
300
200 VC1(V) VCo(V)
100 VC2(V) Scope
0
Io(A)
-100
-200
Load
DSPACE
-300
1202
-400 Power Supply

1.435 1.44 1.445 1.45 1.455 1.46 1.465 1.47 1.475

Time(sec) Laptop
Fig. 5. Inverter Output voltage, capacitors C1, C2, and Co and
output current with R load. 7-Level Power Supply
Single-Phase
Inverter
Fundamental (50Hz) = 18.77 , THD= 47.12%
Fig. 9. Capture of hardware setup.
20
Mag(% of Fundamental)

15
vgs4 10V/div

vgs3 10 V/div
10

vgs2 10 V/div
5

Vgs1 10 V/div) 4 ms/div

0
0 2 4 6 8 10 12 14 16 18 20 Fig. 10. Gate-source pulses for switches S1, S2, S3, and S4 .
Harmonic order
Fig. 6. Total harmonic distortion of R load with no filter
applied. vgs8 10 V/div

Vo(V)
400
vgs7 10 V/div
Vin(V)
300
VC1(V) VCo(V) vgs6 10 V/div
200
100 VC2(V)
0
-100
Io(A) vgs5 10 V/div 4 ms/div
-200
-300
-400

1.565 1.57 1.575 1.58 1.585 1.59 1.595 1.6

Fig. 11. Gate-source pulses for switches S5, S6, S7, and S8.
Time(sec)
Fig. 7. Inverter Output voltage, capacitors C1, C2, and Co and vc1 (10 V/div)
output current with R_L load.
vo (5 V/div)
Fundamental (50Hz) = 16.19 , THD= 22.64%
18

16
Mag(% of Fundamental)

14

12

10
vC2 (10 V/div)
10 ms/div
8

4 Fig. 12. Output voltage, capacitor C1 voltage and capacitor C2

voltage.
2
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