Name: Syed Arham……………………………………………………………………………………………………………………..

Affiliation (Institution/Company):………………………………………………………………………………………….

Email: …………… Phone:…………………………………………

Title of Internship Program Undertaken:……… Design Verification using Verilog ………………

Assignment No and Title ………………………………………………………………………………………………………….

Important Instructions:
1) All assignment results should be computer screenshot or computer typed. Handwritten
and scanned copies shall not be considered for evaluation
2) Due date for all assignment submission is 1 Week from the last date of internship 3) All
assignment questions should be captured along with solutions/answers.
4) Code snippets, simulation results should be captured properly
5) Use only the JPEG image format for capturing the simulation results and name/label the results
appropriately.
6) The description of answers should be short and crisp. Provide only the required information,
answered copied or cut and pasted from google shall not be considered.

PRIVATE & CONFIDENTIAL

Excel VLSI Technologies
1) Design and verify a 4 bit serial adder USER SPACE

module apb_add_master (
input logic pclk,
input logic preset_n,

input logic[1:0] add_i,

output logic psel_o,

output logic penable_o,
output logic [31:0] paddr_o,
output logic pwrite_o,
output logic [31:0] pwdata_o,
input logic [31:0] prdata_i,
input logic pready_i

);

typedef enum logic[1:0] {ST_IDLE, ST_SETUP, ST_ACCESS} apb_state_t;

apb_state_t state_q;
apb_state_t nxt_state;

logic apb_state_setup;
logic apb_state_access;

logic nxt_pwrite;
logic pwrite_q;

logic [31:0] nxt_rdata;

logic [31:0] rdata_q;

always_ff @(posedge pclk or negedge preset_n)

if (~preset_n) state_q <= ST_IDLE;
else
state_q <= nxt_state;

always_comb begin
nxt_pwrite = pwrite_q;
nxt_rdata = rdata_q; case
(state_q) ST_IDLE: if
(add_i[0]) begin
nxt_state = ST_SETUP;
PRIVATE & CONFIDENTIAL
Excel VLSI Technologies
PRIVATE & CONFIDENTIAL
Excel VLSI Technologies
 nxt_pwrite = add_i[1];
end else begin
nxt_state = ST_IDLE;
end
ST_SETUP: nxt_state = ST_ACCESS;
ST_ACCESS:
if (pready_i) begin
if (~pwrite_q)
nxt_rdata = prdata_i;
nxt_state = ST_IDLE;
end else
nxt_state = ST_ACCESS;
default: nxt_state = ST_IDLE;
endcase
end

assign apb_state_access = (state_q == ST_ACCESS);

assign apb_state_setup = (state_q == ST_SETUP);

assign psel_o = apb_state_setup | apb_state_access;

assign penable_o = apb_state_access;

// APB Address
assign paddr_o = {32{apb_state_access}} & 32'hA000;

// APB PWRITE control signal

always_ff @(posedge pclk or negedge preset_n)
if (~preset_n) pwrite_q <= 1'b0;
else
pwrite_q <= nxt_pwrite;

assign pwrite_o = pwrite_q;

assign pwdata_o = {32{apb_state_access}} & (rdata_q + 32'h1);

always_ff @(posedge pclk or negedge preset_n)

if (~preset_n) rdata_q <= 32'h0;
else
rdata_q <= nxt_rdata;

endmodule

PRIVATE & CONFIDENTIAL

Excel VLSI Technologies
CODE FOR TEST BENCH

define CLK @(posedge pclk)

module apb_slave_tb ();

logic pclk;
logic preset_n; // Active low reset

logic[1:0] add_i; // 2'b00 - NOP, 2'b01 - READ, 2'b11 -

WRITE

logic psel_o;
logic penable_o;

logic [31:0] paddr_o;

logic pwrite_o;

logic [31:0] pwdata_o;

logic [31:0] prdata_i;

PRIVATE & CONFIDENTIAL

Excel VLSI Technologies
 logic pready_i;

// Implement clock
always begin pclk
= 1'b0;
#5;
pclk = 1'b1;
#5;
end

apb_add_master APB_MASTER (.*);

initial begin
preset_n = 1'b0;
add_i = 2'b00;
repeat (2) `CLK;
preset_n = 1'b1;
repeat (2) `CLK;

add_i = 2'b01;
`CLK; add_i
= 2'b00;
repeat (4) `CLK;

add_i = 2'b11;
`CLK; add_i =
2'b00; repeat
(4) `CLK;

PRIVATE & CONFIDENTIAL

Excel VLSI Technologies
 $finish();
end

always_ff @(posedge pclk or negedge preset_n)

begin if (~preset_n) pready_i <= 1'b0; else
begin
if (psel_o && penable_o) begin
pready_i <= 1'b1;
prdata_i <= $urandom%32'h20;
end else begin
pready_i <= 1'b0;
prdata_i <=
$urandom%32'hFF; end end
end

initial begin
$dumpfile("apb_master.vcd");
$dumpvars(2, apb_slave_tb); end

endmodule

PRIVATE & CONFIDENTIAL

Excel VLSI Technologies
 USER SPACE

WAVE FORMS

PRIVATE & CONFIDENTIAL

Excel VLSI Technologies
 2)Design RTL for APB protocal based memory USER SPACE

module serial_adder(input clk, input reset, input in1, input in2, output reg[3:0] sum, output reg

carry_out); reg[3:0] register_sum; reg carry_in;

always @(posedge clk) begin

if (reset) begin carry_in <= 1'b0;

register_sum <= 4'b0000; end else begin

register_sum <= register_sum + {carry_in, in1, in2};

carry_in <= register_sum[4]; end end

assign sum = register_sum[3:0];

assign carry_out = register_sum[4];

endmodule

PRIVATE & CONFIDENTIAL

Excel VLSI Technologies
 USER SPACE

CODE FOR TEST BENCH

module testbench();

reg clk, reset, in1, in2; wire [3:0] sum; wire carry_out; serial_adder dut(.clk(clk),

.reset(reset), .in1(in1), .in2(in2), .sum(sum), .carry_out(carry_out)); initial begin

$dumpfile("dump.vcd");

$dumpvars(0, testbench); end

initial begin

clk = 0;

reset = 1; in1

= 4'b0000;

in2 = 4'b0000;

#10 reset = 0;

in1 = 4'b0000;

in2 = 4'b0000;

#10 $display("sum = %b, carry_out = %b", sum, carry_out); if

(sum != 4'b0000 || carry_out != 1'b0) $error("Test case 1 failed!");

in1 = 4'b0001;

in2 = 4'b0001;

#10 $display("sum = %b, carry_out = %b", sum, carry_out); if

(sum != 4'b0010 || carry_out != 1'b0) $error("Test case 2 failed!");
in1 = 4'b0111; in2 = 4'b0001;

PRIVATE & CONFIDENTIAL

Excel VLSI Technologies
PRIVATE & CONFIDENTIAL
Excel VLSI Technologies
 #10 $display("sum = %b, carry_out = %b", sum, carry_out); if

(sum != 4'b1000 || carry_out != 1'b0) $error("Test case 3 failed!");

in1 = 4'b0111;

in2 = 4'b1000;

#10 $display("sum = %b, carry_out = %b", sum, carry_out); if

(sum != 4'b1111 || carry_out != 1'b0) $error("Test case 4 failed!");

in1 = 4'b1111; in2 = 4'b0001;

#10 $display("sum = %b, carry_out = %b", sum, carry_out); if

(sum != 4'b0000 || carry_out != 1'b1) $error("Test case 5 failed!");

$display("All tests passed!");

$finish; end

always #5 clk =

~clk;

endmodule

PRIVATE & CONFIDENTIAL

Excel VLSI Technologies
WAVE FORMS

PRIVATE & CONFIDENTIAL

Excel VLSI Technologies