UTILIZATION REPORT:

POWER REPORT:

TIMING REPORT:
POST IMPLEMENTATION/POST SYNTHESIS SIMULATION:

IMPLEMENTED DEVICE:
SYNTHESIZED DESIGN:

CONSTRAINT FILE:
SIMULATION WAVEFORM:

ELABORATED DESIGN:
PROGRAM CODE:

module seq_0110(clk,rst,inp,outp,q);
input clk,rst,inp;
output reg outp;
output q;
reg [1:0]state;
parameter S0=0,S1=1,S2=2,S3=3;
div d1(clk,rst,q);
always @(posedge clk or posedge rst)
if(rst)
  begin
   state<=S0;
   outp<=0;
   end
   else
   case(state)
   S0:if(inp)
   begin
   state<=S0;
   outp<=0;
   end
   else
   begin
   state<=S1;
   outp<=0;
   end
    S1:if(inp)
    begin
    state<=S2;
    outp<=0;
    end
    else
    begin
    state<=S1;
    outp<=0;
    end
      S2:if(inp)
     begin
     state<=S0;
     outp<=0;
     end
     else
     begin
     state<=S3;
     outp<=0;
     end
       S3:if(inp)
      begin
      state<=S0;
      outp<=1;
      end
      else
      begin
      state<=S1;
      outp<=0;
      end
      default:outp<=0;
      endcase  
 
endmodule

module div(clk,rst,clknew);
    input clk,rst;
    output reg clknew;
    reg [29:0]sig;
    always @(posedge rst or posedge clk)
    begin
     if(rst==1)
      sig<=0;
    else
    begin
     sig<=sig+1;
     clknew<=sig[27];
     end
    end
endmodule