INSTITUTO POLITÉCNICO NACIONAL

INSTITUTO POLITECNICO NACIONAL

ESCUELA SUPERIOR DE COMPUTO

Diseño de sistemas digitales

Practica

7
Aplicaciones con contadores

• Espinosa Vergara David Daniel

• Nayeli García
Análisis
Código
a. Código en VHD
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity Dado is Port (

clk,clr, e : in std_logic;
display: out std_logic_vector(6 downto 0)
);
end Dado;

architecture aDado of Dado is

signal aux : std_logic_vector(2 downto 0);
begin
process (clk, clr)
begin
if (clr='1') then
aux <= "001";
elsif (rising_edge(clk)) then
if (e='1') then
aux <= aux + "001";
if (aux = "110") then
aux <= "001";
end if;
end if;
end if;
end process;
with aux select display <=
"1001111" when "001",
"0010010" when "010",
"0000110" when "011",
"1001100" when "100",
"0100100" when "101",
"0100000" when "110",
"1001111" when others;

end architecture;
 b. Capturas en Galaxy

c. Capturas en Proteus

B. Codigo
a. Código en VHD
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity boleta is Port (

clk,clr, e : in std_logic;
display: out std_logic_vector(6 downto 0)
);
end boleta;

architecture aBoleta of boleta is

constant q0: std_logic_vector(6 downto 0) := "0000001";

constant q1: std_logic_vector(6 downto 0) := "1001111";
constant q2: std_logic_vector(6 downto 0) := "0010010";
constant q3: std_logic_vector(6 downto 0) := "0000110";
constant q4: std_logic_vector(6 downto 0) := "1001100";
constant q5: std_logic_vector(6 downto 0) := "0100100";
constant q6: std_logic_vector(6 downto 0) := "0100000";
constant q7: std_logic_vector(6 downto 0) := "0001111";
constant q8: std_logic_vector(6 downto 0) := "0000000";
constant q9: std_logic_vector(6 downto 0) := "0000100";
constant qA: std_logic_vector(6 downto 0) := "0001000";
constant qB: std_logic_vector(6 downto 0) := "1100000";
constant qC: std_logic_vector(6 downto 0) := "0110001";
constant qD: std_logic_vector(6 downto 0) := "1000010";
 constant qE: std_logic_vector(6 downto 0) := "0110000";
constant qF: std_logic_vector(6 downto 0) := "0111000";

signal aux : std_logic_vector(6 downto 0);

begin

process (clk, clr)

begin
if (clr='1') then
aux <= q0;
elsif (rising_edge(clk)) then
if (e='1') then
case aux is
when q0 => aux <= q1;
when q1 => aux <= q2;
when q2 => aux <= q3;
when q3 => aux <= q4;
when q4 => aux <= q5;
when q5 => aux <= q6;
when q6 => aux <= q7;
when q7 => aux <= q8;
when q8 => aux <= q9;
when q9 => aux <= qA;
when qA => aux <= qB;
when qB => aux <= qC;
when qC => aux <= qD;
when qD => aux <= qE;
when qE => aux <= qF;
when qF => aux <= q0;
when others => aux <= q0;
end case;
end if;
end if;
end process;
display <= aux;
end architecture;

b. Capturas en Galaxy
 c. Capturas en Proteus

C. Codigo
a. Código en VHD
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity Nombre is Port (

clk,clr, e : in std_logic;
display: out std_logic_vector(6 downto 0)
);
end Nombre;

architecture aNombre of Nombre is

constant m0: std_logic_vector(1 downto 0) := "00";
constant m1: std_logic_vector(1 downto 0) := "01";
constant m2: std_logic_vector(1 downto 0) := "10";

constant nd: std_logic_vector(6 downto 0) := "1000010";

constant ni: std_logic_vector(6 downto 0) := "1001111";
constant ns: std_logic_vector(6 downto 0) := "0100100";
constant ne: std_logic_vector(6 downto 0) := "0110000";
constant nn: std_logic_vector(6 downto 0) := "0101010";
constant no: std_logic_vector(6 downto 0) := "0000001";
constant ng: std_logic_vector(6 downto 0) := "0000100";
constant nt: std_logic_vector(6 downto 0) := "1110000";
constant na: std_logic_vector(6 downto 0) := "0001000";
constant nl: std_logic_vector(6 downto 0) := "1110001";
 constant q0 : std_logic_vector(8 downto 0) := m0&nd;
constant q1 : std_logic_vector(8 downto 0) := m0&ni;
constant q2 : std_logic_vector(8 downto 0) := m0&ns;
constant q3 : std_logic_vector(8 downto 0) := m0&ne;
constant q4 : std_logic_vector(8 downto 0) := m0&nn;
constant q5 : std_logic_vector(8 downto 0) := m0&no;
constant q6 : std_logic_vector(8 downto 0) := m1&nd;
constant q7 : std_logic_vector(8 downto 0) := m1&ni;
constant q8 : std_logic_vector(8 downto 0) := m0&ng;
constant q9 : std_logic_vector(8 downto 0) := m2&ni;
constant q10 : std_logic_vector(8 downto 0) := m0&nt;
constant q11 : std_logic_vector(8 downto 0) := m0&na;
constant q12 : std_logic_vector(8 downto 0) := m0&nl;

signal aux : std_logic_vector(8 downto 0);

begin

process (clk, clr)

begin
if (clr='1') then
aux <= q0;
elsif (rising_edge(clk)) then
if (e='1') then
case aux is
when q0 => aux <= q1;
when q1 => aux <= q2;
when q2 => aux <= q3;
when q3 => aux <= q4;
when q4 => aux <= q5;
when q5 => aux <= q6;
when q6 => aux <= q7;
when q7 => aux <= q8;
when q8 => aux <= q9;
when q9 => aux <= q10;
when q10 => aux <= q11;
when q11 => aux <= q12;
when q12 => aux <= q0;
when others => aux <= q0;
end case;
end if;
end if;
end process;
display <= aux(6 downto 0);
end architecture;

b. Capturas en Galaxy
 c. Capturas en Proteus

D. Codigo
a. Código en VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity boleta is Port (

clk,clr, e : in std_logic;
display: out std_logic_vector(6 downto 0)
);
end boleta;

architecture aBoleta of boleta is

constant m0: std_logic_vector(1 downto 0) := "00";
constant m1: std_logic_vector(1 downto 0) := "01";
constant m2: std_logic_vector(1 downto 0) := "10";

constant n2: std_logic_vector(6 downto 0) := "0010010";

constant n0: std_logic_vector(6 downto 0) := "0000001";
constant n1: std_logic_vector(6 downto 0) := "1001111";
constant n6: std_logic_vector(6 downto 0) := "0100000";
constant n3: std_logic_vector(6 downto 0) := "0000110";
constant n5: std_logic_vector(6 downto 0) := "0100100";

constant q0 : std_logic_vector(8 downto 0) := m0&n2;

constant q1 : std_logic_vector(8 downto 0) := m0&n0;
constant q2 : std_logic_vector(8 downto 0) := m1&n2;
constant q3 : std_logic_vector(8 downto 0) := m1&n0;
constant q4 : std_logic_vector(8 downto 0) := m0&n6;
constant q5 : std_logic_vector(8 downto 0) := m0&n3;
constant q6 : std_logic_vector(8 downto 0) := m2&n0;
constant q7 : std_logic_vector(8 downto 0) := m0&n1;
constant q8 : std_logic_vector(8 downto 0) := m2&n2;
constant q9 : std_logic_vector(8 downto 0) := m0&n5;

signal aux : std_logic_vector(8 downto 0);

begin

process (clk, clr)

begin
if (clr='1') then
aux <= q0;
elsif (rising_edge(clk)) then
if (e='1') then
case aux is
when q0 => aux <= q1;
when q1 => aux <= q2;
when q2 => aux <= q3;
when q3 => aux <= q4;
when q4 => aux <= q5;
when q5 => aux <= q6;
when q6 => aux <= q7;
when q7 => aux <= q8;
when q8 => aux <= q9;
when q9 => aux <= q0;
when others => aux <= q0;
end case;
end if;
end if;
end process;
display <= aux(6 downto 0);
end architecture;

b. Capturas en Galaxy

c. Capturas en Proteus
Conclusion:

Se ha llegado a una conclusión bastante útil, pues la codificación de un contador con código
de usuario es por mucho la forma más fácil solo se debe asignar constantes y cumplir por
medio where la forma del autómata que queremos, por otro lado tenemos el método con
las fórmulas aplicadas, esto podría ser un poco más difícil puesto que las fórmulas podrían
no ser las correctas, o no estas simplificadas provocando una extensión de código mayor
a nuestro método anterior.
Se ha logrado ver con éxito contadores hexadecimales, decimales, con un texto especifico
o números en especifico