Práctica: BCD con Contador en VHDL

Grupo D
Mesa: #4

Procedimiento:
Testbench:

-- Code your testbench here

library IEEE;
use IEEE.std_logic_1164.all;

entity testbench is
-- empty
end testbench;

architecture tb of testbench is
component GeneradorParidadPar3bInst IS
PORT ( svEntrada: IN std_logic_vector(2 DOWNTO 0);
sSalida: OUT std_logic);
end component;

signal svEntrada_in: std_logic_vector(2 downto 0);

signal sSalida_out : std_logic;
begin

DUT: GeneradorParidadPar3bInst port map(svEntrada_in, sSalida_out);

process
begin

svEntrada_in <="000";
wait for 1 ns;
 assert(sSalida_out = '0') report "fallo 1" severity error;

svEntrada_in <="001";
wait for 1 ns;
assert(sSalida_out = '1') report "fallo 2" severity error;

svEntrada_in <="010";
wait for 1 ns;
assert(sSalida_out = '1') report "fallo 3" severity error;

svEntrada_in <="011";
wait for 1 ns;
assert(sSalida_out = '0') report "fallo 4" severity error;

svEntrada_in <="100";
wait for 1 ns;
assert(sSalida_out = '1') report "fallo 5" severity error;

svEntrada_in <="101";
wait for 1 ns;
assert(sSalida_out = '0') report "fallo 6" severity error;

svEntrada_in <="110";
wait for 1 ns;
assert(sSalida_out = '0') report "fallo 7" severity error;

svEntrada_in <="111";
wait for 1 ns;
assert(sSalida_out = '1') report "fallo 8" severity error;

assert false report "test done." severity note;

wait;
end process;
end tb;

Design:

-- Code your design here

library IEEE;
use IEEE.std_logic_1164.all;

--=======================================================
-- Declaración de la entidad y arquitectura del generador.
--=======================================================
ENTITY GeneradorParidadPar3bInst IS
 PORT ( svEntrada: IN std_logic_vector(2 DOWNTO 0);
sSalida: OUT std_logic);
END GeneradorParidadPar3bInst;

ARCHITECTURE GeneradorParidadPar3bArch2 OF GeneradorParidadPar3bInst IS

-- Se declara el uso de componentes tipo XOR2.
COMPONENT XOR2
--Se indica los puertos que tiene el componente.
PORT( sE1, sE2: IN std_logic;
sS: OUT std_logic);
END COMPONENT;

-- Se declaran señales adicionales de trabajo.

SIGNAL sX1, sX2: std_logic;
BEGIN --Comienzo de la arquitectura.
G1: XOR2 PORT MAP(sE1=>svEntrada(0), sE2=>svEntrada(1), sS=>sX1);
G2: XOR2 PORT MAP(sE1=>svEntrada(2), sE2=>'0', sS=>sX2);
G3: XOR2 PORT MAP(sE1=>sX1, sE2=>sX2, sS=>sSalida);
END GeneradorParidadPar3bArch2;

Resultados:

Análisis:
El generador de paridad de 3 bits esta correctamente implementado y da los resultados
esperados.