DSD LAB REPORTS

Lab # 11: This Lab has been designed to familiarize with the design of a keypad Scanner
using VHDL and show the output on the FPGA board

Objectives:
• The objective of this lab is to design a scanner for a telephone keypad using VHDL
Required Equipment:
Hardware: FPGA design board
Software: Quartus II
Methodology:

• The keypad is wired in matrix form with a switch at the intersection of each row and column.
• Pressing a key establishes a connection between a row and column.
• The purpose of the scanner is to determine which key has been pressed and output a binary number, which
corresponds to the key number.
• The lab task also contained a truth table that corresponded to the keys on the keypad.
• The lab task included drawing the fsm, coding and then verifying the operation of the of the keypad
scanner using Quartus simulator.

• The code was to be implemented. Observations were to be made and the results were to be verified.

TASK 1: Keypad scanner

1. In this lab task, I implemented a VHDL code for keypad scanner on Quartus II software by using
VHDL.
2. Verified the output of the code from Vwf waveform.

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity lab11 is
port(
clock: in std_logic;
init: in std_logic;
reset: in std_logic;
kd,k,v: in std_logic;
Y: out string (1 to 1);
Y1: out string (1 to 6);
Y2: out string (1 to 2);
Y3: out string (1 to 2);
Y4: out string (1 to 2);
Y5: out string (1 to 6)
);
end lab11;
architecture behav of lab11 is
type state_type is(s0,s1,s2,s3,s4,s5);
signal state: state_type;

Done By: Shermeen Tajammal

DSD LAB REPORTS

begin
next_state_logic: process (clock,reset)
begin
if(clock'event and clock = '1') then
case state is
when s0 =>
if init = '1' then
state <= s1;
end if;
when s1 =>
if kd = '1' then
state <= s2;
else
state <= s1;
end if;
when s2 =>
if k = '0' then
state <= s3;
elsif (k = '1' and v ='1') then
state <= s5;
end if;
when s3 =>
if k ='0' then
state <= s4;
elsif (k= '1' and v = '1') then
state <= s5;
end if;
when s4 =>
if v = '1' then
state <= s5;
end if;
when s5=>
if kd = '1' then
state <= s5;
else
state <= s1;
end if;
end case;
end if;
end process;
output_logic: process(state)
begin
case state is
when s0 =>
Y <= "0" ;
when s1 =>
Y1 <= "c0c1c2";
when s2 =>
Y2 <= "c0";
when s3 =>
Y3 <= "c1";
when s4 =>
Y4 <= "c2";

Done By: Shermeen Tajammal

 DSD LAB REPORTS

when s5 =>
Y5 <= "c0c1c2";
end case;
end process;
end behav;

Vwf Result:

Sir please help me in this output

Figure 1: Vwf Results of Task1

Task 2: Decoder

Vwf Result:

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity decode38a is
port(
R0,R1,R2,R3,C0,C1,C2: in std_logic;
N0,N1,N2,N3: out std_logic
);
end decode38a;
architecture behav of decode38a is
begin

Done By: Shermeen Tajammal

 DSD LAB REPORTS

process (R0,R1,R2,R3,C0,C1,C2)
begin
N3<=(R2 and (not C0)) or (R3 and (not C1));
N2<=(R1) or (R2 and C0);
N1<=(R0 and (not C0)) or (C2 and (not R2)) or ((not R1) and (not R0)and C0);
N0<=(R1 and C1) or (C2 and (not R1)) or ((not R3) and (not R1) and (not C1));
end process;
end behav;

Conclusion:
In this lab, keypad scanner was studied in detail. We implemented it using VHDL on Quartus II software and
verified its result on FPGA board.

Done By: Shermeen Tajammal