Instituto Tecnológico de Santo Domingo

Materia:
Fundamentos Electrónica Digital
Profesor:
Yobany Díaz Roque
Estudiante:
Sebastian Martinez Madera
ID:
1101499
 Implementar en VHDL el sumador parametrizado y la ALU

Design.vhd:

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

ENTITY design IS

PORT (

EntradaA, EntradaB : IN std_logic_vector(3 DOWNTO 0);

Resultado : OUT std_logic_vector(4 DOWNTO 0);

reset, clk, I_ALU, OP_ALU, ID_Flag: IN std_logic;

Flagd: OUT std_logic

);

END design;

ARCHITECTURE designArch OF design IS

--Señales internas del Sistema

signal svRealB: std_logic_vector(3 DOWNTO 0);

signal sZero: std_logic;

-- Componente Mux

COMPONENT Mux

port(
sInALU: IN std_logic;

svEntradaB:IN std_logic_vector(3 DOWNTO 0);

svRealB:OUT std_logic_vector(3 DOWNTO 0)

);

END COMPONENT;

-- Componente OpALU

COMPONENT OpALU is

port(

sOpALU: IN std_logic;

svEntradaA:IN std_logic_vector(3 DOWNTO 0);

svResultMux:IN std_logic_vector(3 DOWNTO 0);

svResultado:OUT std_logic_vector(4 DOWNTO 0);

sZero: OUT std_logic

);

END COMPONENT;

-- Componente Flag

COMPONENT Flag is

port(

sCLK, sResetL, sIdFlag, sZero: IN std_logic;

sFlag: OUT std_logic

);

END COMPONENT;
SIGNAL sX: std_logic_vector(3 DOWNTO 0);

SIGNAL sXZero: std_logic;

BEGIN

Multiplexor: Mux PORT MAP(sInALU => I_ALU, svEntradaB => EntradaB, svRealB =>
sX);

ALU: OpALU PORT MAP(sOpALU => OP_ALU, svEntradaA => EntradaA, svResultMux
=> sX, svResultado => Resultado, sZero => sXZero);

FlagComp: Flag PORT MAP(sCLK => clk, sResetL => reset, sIdFlag => ID_Flag, sFlag
=> Flagd, sZero => sXZero);

END designArch;

Mux.vhd:

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

--Necesaria para el operador &

use IEEE.std_logic_unsigned.all;

ENTITY Mux IS

PORT (

--Asociadas al Multiplexor.

sInALU: IN std_logic;

svEntradaB:IN std_logic_vector(3 DOWNTO 0);

svRealB:OUT std_logic_vector(3 DOWNTO 0)

 );

END Mux;

ARCHITECTURE MuxArch of Mux IS

BEGIN

PROCESS (sInALU,svEntradaB)

BEGIN

IF (sInALU = '0')

THEN svRealB <= svEntradaB;

--Asignación de 0 a un vector con OTHERS.

ELSE svRealB <= (OTHERS => '0');

END IF;

END PROCESS;

END MuxArch;

OpALU.vhd:

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

ENTITY opALU IS

PORT (

--Asociadas a la ALU.

sOpALU: IN std_logic;
 svEntradaA:IN std_logic_vector(3 DOWNTO 0);

svResultMux:IN std_logic_vector(3 DOWNTO 0);

svResultado:OUT std_logic_vector(4 DOWNTO 0);

sZero: OUT std_logic

);

END opALU;

ARCHITECTURE OpALUArch OF opALU IS

BEGIN

PROCESS (svEntradaA, sOpALU, svResultMux)

--Variables auxiliares del proceso en curso.

VARIABLE svVarAUx: std_logic_vector(4 DOWNTO 0);

BEGIN

sZero <= '0';

--Se efectúa la operación indicada por la

--señal sOpALU:

IF (sOpALU = '0')

-- Generación de un resultado de 5 bits a partir de

-- 4 bits mediante el uso del operador concatenación (&).

THEN svVarAUx := ('0'&svEntradaA) + ('0'&svResultMux);

ELSE svVarAUx := ('0'&svEntradaA) - ('0'&svResultMux);

--Se actualiza la salida de la ALU.

END IF;

svResultado <= svVarAUx;

 IF (svVarAUx = "00000")

THEN sZero <= '1';

END IF;

END PROCESS;

END OpALUArch;

Flag.vhd:

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

ENTITY Flag IS

PORT (--Asociadas al indicador de Flag.

sCLK, sResetL, sIdFlag, sZero: IN std_logic;

sFlag: OUT std_logic

);

END Flag;

ARCHITECTURE FlagArch OF Flag IS

BEGIN

PROCESS(sResetL,sClk,sIdFlag,sZero)
 BEGIN

IF (sResetL = '0')

THEN sFlag <= '0';

-- Flanco ascendente de reloj. Se verá con detalle en

-- el próximo tema.

ELSIF (sCLK'event and sCLK = '1')

THEN IF (sIdFlag = '1')

THEN sFlag <= sZero;

END IF;

END IF;

END PROCESS;

END FlagArch;

Testbench.vhd:

-- Testbench for GeneradorParidadPar3bInst

library IEEE;

use IEEE.std_logic_1164.all;

entity testbench is

-- empty

end testbench;

architecture tb of testbench is

-- DUT component
component design IS

PORT (

EntradaA, EntradaB : IN std_logic_vector(3 DOWNTO 0);

Resultado : OUT std_logic_vector(4 DOWNTO 0);

reset, clk, I_ALU, OP_ALU, ID_Flag: IN std_logic;

Flagd: OUT std_logic

);

end component;

signal EntradaA_in, EntradaB_in : std_logic_vector(3 DOWNTO 0);

signal Resultado_out : std_logic_vector(4 DOWNTO 0);

signal reset_in, clk_in, I_ALU_in, OP_ALU_in, ID_Flag_in: std_logic;

signal Flagd_out: std_logic;

begin

-- Connect DUT

DUT: design port map(EntradaA => EntradaA_in, EntradaB => EntradaB_in, Resultado
=> Resultado_out, reset => reset_in, clk => clk_in, I_ALU => I_ALU_in, OP_ALU =>
OP_ALU_in, ID_Flag => ID_Flag_in, Flagd => Flagd_out );

process

begin

EntradaA_in <= "1010";

EntradaB_in <= "0001";

reset_in <= '0';

clk_in <= '0';

I_ALU_in <= '0';

OP_ALU_in <= '0';

ID_Flag_in <= '0';

wait for 1 ns;

EntradaA_in <= "1010";

EntradaB_in <= "0001";

reset_in <= '0';

clk_in <= '0';

I_ALU_in <= '0';

OP_ALU_in <= '1';

ID_Flag_in <= '0';

wait for 1 ns;

EntradaA_in <= "0011";

EntradaB_in <= "0101";

reset_in <= '0';

clk_in <= '0';

I_ALU_in <= '0';

OP_ALU_in <= '0';

ID_Flag_in <= '0';

wait for 1 ns;

 EntradaA_in <= "0011";

EntradaB_in <= "0101";

reset_in <= '0';

clk_in <= '0';

I_ALU_in <= '0';

OP_ALU_in <= '1';

ID_Flag_in <= '0';

wait for 1 ns;

assert false report "Test done." severity note;

wait;

end process;

end tb;