https://www.youtube.com/watch?

v=maoLsSSRecA

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fadd is
port(
A:IN STD_LOGIC;
B:IN STD_LOGIC;
cin:IN STD_LOGIC;
sum:out std_logic;
carry:out std_logic
);
end fadd;

architecture arch_fa of fadd is

signal temp1,temp2,temp3:std_logic;

component HAdd is
port(
a,b:IN std_logic;
c,s:OUT std_logic
);
end component;

component OR1 is
port(
p,q:in std_logic;
r:out std_logic
);
end component;

begin

HA1:HAdd port map(a=>A,b=>B,c=>temp1,s=>temp2);

HA2:HAdd port map(a=>temp2,b=>cin,c=>temp3,s=>sum);
ORG:OR1 port map(p=>temp1,q=>temp3,r=>carry);

end arch_fa;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity HAdd is
port(
a,b:IN std_logic;
c,s:OUT std_logic
);
end HAdd;

architecture arch_HA of HAdd is

begin
s<= A xor B;
c<= A AND B;
end arch_HA;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity OR1 is
port(
p,q:IN std_logic;
r:OUT std_logic
);
end OR1;

architecture arch_OR1 of OR1 is

begin
r<= p OR q;
end arch_OR1;

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>>>>>>>
testbench
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>>>>>>>

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY fadd_tb IS
END fadd_tb;

ARCHITECTURE behavior OF fadd_tb IS

COMPONENT fadd
PORT(
A : IN std_logic;
B : IN std_logic;
cin : IN std_logic;
sum : OUT std_logic;
carry : OUT std_logic
);
END COMPONENT;

signal A : std_logic := '0';

signal B : std_logic := '0';
signal cin : std_logic := '0';

signal sum : std_logic;

signal carry : std_logic;

BEGIN
 uut: fadd PORT MAP (
A => A,
B => B,
cin => cin,
sum => sum,
carry => carry
);

stim_proc_A: process
begin
A<='1';
wait for 100 ns;
A<='0';
wait;
end process;

stim_proc_B: process
begin
B<='1';
wait;
end process;

stim_proc_cin: process
begin
cin<='0';
wait for 100 ns;
cin<='1';
wait;
end process;
END;