CIRCUITO 1:

ENTITY ciruno IS
PORT(
a,b :IN BIT;
c,d :OUT BIT);
END ciruno;
ARCHITECTURE arch_uno OF ciruno IS
BEGIN
c <= (a OR b)AND(NOT(a AND b));
d <= (NOT a)AND b;
END arch_uno;

Test Bench circuito 1:

ENTITY tb_ciruno IS
END tb_ciruno;
ARCHITECTURE arch_uno OF tb_ciruno IS
COMPONENT ciruno IS
PORT(
a,b :IN BIT;
c,d :OUT BIT);
END COMPONENT ciruno;
SIGNAL ent1:bit:='0';
SIGNAL ent2:bit:='0';
SIGNAL sal1:bit;
SIGNAL sal2:bit;
BEGIN
ckt1:ciruno
PORT MAP
(
a=> ent1,
b=> ent2,
c=> sal1,
d=> sal2

);
PROCESS
BEGIN
WAIT FOR 2 ms;
ent2 <= '1';
WAIT FOR 2 ms; -- La entrada b completa su primer ciclo (4 ms)
ent2 <='0';
ent1 <='1';
WAIT FOR 2 ms;
ent2 <='1';
WAIT FOR 2 ms; -- La entrada a completa su primer ciclo (8 ms)
ent2 <='0';
ent1 <='0'; --A partir de aqu se repetirn los ciclos a hasta el tiempo que
ms convenga, en este ejercicio se lleg hasta 80 ms.
END PROCESS;
END ARCHITECTURE arch_uno;

Test Bench para la tabla de verdad:

ENTITY tb_cirunod IS
END tb_cirunod;
ARCHITECTURE arch_unod OF tb_cirunod IS
COMPONENT cirunod IS
PORT(
a,b :IN BIT;
c,d :OUT BIT);
END COMPONENT cirunod;
SIGNAL ent1:bit:='0';
SIGNAL ent2:bit:='0';
SIGNAL sal1:bit;
SIGNAL sal2:bit;
BEGIN
ckt1:cirunod

PORT MAP
(
a=> ent1,
b=> ent2,
c=> sal1,
d=> sal2
);
PROCESS
BEGIN
WAIT FOR 20 ns;
ent2 <= '1';
wait for 20 ns;
ent2 <='0';
ent1 <='1';
wait for 20 ns;
ent1 <='1';
END PROCESS;
END ARCHITECTURE arch_unod;
CIRCUITO 2:
ENTITY cirdos IS
PORT(
A,B,C,D :IN BIT;
x,y,z :OUT BIT);
END cirdos;
ARCHITECTURE arch_dos OF cirdos IS
BEGIN
x <= (((NOT A)AND(NOT B))AND(C AND D)) OR ((NOT
A)AND(B AND (NOT D))) OR (A AND (NOT B) AND (NOT D));
y <= ((NOT A)AND B AND (NOT C) AND D) OR ((NOT A) AND B
AND C AND (NOT D)) OR (A AND (NOT B) AND C AND D) OR (A
AND (NOT C) AND (NOT D));

z <= ((NOT A)AND B AND C AND D) OR (A AND (NOT B) AND

(NOT C) AND D) OR (A AND (NOT B) AND C AND (NOT D)) OR (B
AND (NOT C) AND (NOT D));
END arch_dos;

TEST CIRCUITO2:
ENTITY tb_cirdos IS
END tb_cirdos;
ARCHITECTURE arch_dos OF tb_cirdos IS
COMPONENT cirdos IS
PORT(
a,b,c,d :IN BIT;
x,y,z :OUT BIT);
END COMPONENT cirdos;
SIGNAL ent1:bit:='0';
SIGNAL ent2:bit:='0';
SIGNAL ent3:bit:='0';
SIGNAL ent4:bit:='0';
SIGNAL sal1:bit;
SIGNAL sal2:bit;
SIGNAL sal3:bit;
BEGIN
ckt1:cirdos
PORT MAP
(
a=> ent1,
b=> ent2,
c=> ent3,

d=> ent4,
x=> sal1,
y=> sal2,
z=> sal3
);
PROCESS
BEGIN
WAIT FOR 0.5 ms;
ent1 <='1';
WAIT FOR 0.5 ms;
ent1 <='0';
ent2 <='1';
wait for 0.5 ms;
ent1 <='1';
wait for 0.5 ms;
ent1 <='0';
ent2 <='0';
ent3 <='1';
wait for 0.5 ms;
ent1 <='1';
wait for 0.5 ms;
ent1 <='0';
ent2 <='1';
wait for 0.5 ms;
ent1 <='1';
wait for 0.5 ms;
ent1 <='0';
ent2 <='0';
ent3 <='0';
ent4 <='1';
WAIT FOR 0.5 ms;
ent1 <='1';
WAIT FOR 0.5 ms;
ent1 <='0';
ent2 <='1';

wait for 0.5 ms;

ent1 <='1';
wait for 0.5 ms;
ent1 <='0';
ent2 <='0';
ent3 <='1';
wait for 0.5 ms;
ent1 <='1';
wait for 0.5 ms;
ent1 <='0';
ent2 <='1';
wait for 0.5 ms;
ent1 <='1';
wait for 0.5 ms;
ent1 <='0';
ent2 <='0';
ent3 <='0';
ent4 <='0'; -- En este tiempo todas las variables han completado
al menos ya un ciclo, para obtener un anlisis mas detallado de todas
las combinaciones basta con repetir esta porcin de cdigo las veces
que se quiera, en este ejercicio llegamos hasta un tiempo de 80 ms (8
repeticiones)
END PROCESS;
END ARCHITECTURE arch_dos;

TEST TABLA DE VERDAD:

ENTITY tb2_cirdos IS
END tb2_cirdos;

ARCHITECTURE arch_dos OF tb2_cirdos IS

COMPONENT cirdos IS
PORT(
a,b,c,d :IN BIT;
x,y,z :OUT BIT);
END COMPONENT cirdos;
SIGNAL ent1:bit:='0';
SIGNAL ent2:bit:='0';
SIGNAL ent3:bit:='0';
SIGNAL ent4:bit:='0';
SIGNAL sal1:bit;
SIGNAL sal2:bit;
SIGNAL sal3:bit;
BEGIN
ckt1:cirdos
PORT MAP
(
a=> ent1,
b=> ent2,
c=> ent3,
d=> ent4,
x=> sal1,
y=> sal2,
z=> sal3
);
PROCESS
BEGIN
WAIT FOR 20 ns;
ent4 <='1';
wait for 20 ns;
ent4 <='0';
ent3 <='1';

wait for 20 ns;

ent4 <='1';
wait for 20 ns;
ent4 <='0';
ent3 <='0';
ent2 <='1';
wait for 20 ns;
ent4 <='1';
wait for 20 ns;
ent4 <='0';
ent3 <='1';
wait for 20 ns;
ent4 <='1';
wait for 20 ns;
ent4 <='0';
ent3 <='0';
ent2 <='0';
ent1 <='1';
wait for 20 ns;
ent4 <='1';
wait for 20 ns;
ent4 <='0';
ent3 <='1';
wait for 20 ns;
ent4 <='1';
wait for 20 ns;
ent4 <='0';
ent3 <='0';
ent2 <='1';
wait for 20 ns;
ent4 <='1';
wait for 20 ns;
ent4 <='0';
ent3 <='1';
wait for 20 ns;
ent4 <='1';

END PROCESS;
END ARCHITECTURE arch_dos;

CIRCUITO 3:
ENTITY cir3 IS
PORT(
A,B,C,D,cont :IN BIT;
w,x,y,z :OUT BIT);
END cir3;
ARCHITECTURE arch_3 OF cir3 IS
BEGIN
w <= ((NOT(A)) AND B AND C) OR (A AND (NOT(B)) AND (NOT
C)) OR ( (NOT A) AND B AND (NOT C) AND D);
x <= ((NOT A) AND B AND (NOT C) AND (NOT D)) OR ((NOT A)
AND B AND C AND cont) OR (A AND (NOT B) AND (NOT C) AND D)
OR (A AND (NOT B) AND (NOT C) AND cont);
y <= ((NOT A) AND (NOT B) AND C) OR (A AND (NOT B) AND
(NOT C) AND (NOT D)) OR (A AND (NOT B) AND (NOT C) AND cont)
OR ((NOT A) AND B AND (NOT C) AND D AND cont) OR ((NOT A)
AND B AND C AND D AND (NOT cont));
z <= ((NOT A) AND (NOT B) AND D) OR ((NOT A) AND (NOT C)
AND D AND cont) OR ((NOT A) AND B AND C AND D AND cont) OR
((NOT A) AND B AND C AND (NOT D) AND (NOT cont)) OR (A AND
(NOT B) AND (NOT C) AND D AND cont) OR (A AND (NOT B) AND
(NOT C) AND (NOT D) AND (NOT cont));
END arch_3;
TEST CIRCUITO 3:
ENTITY tb_cir3 IS

END tb_cir3;
ARCHITECTURE arch_3 OF tb_cir3 IS
COMPONENT cir3 IS
PORT(
A,B,C,D,cont :IN BIT;
w,x,y,z :OUT BIT);
END COMPONENT cir3;
SIGNAL ent1:bit:='0';
SIGNAL ent2:bit:='0';
SIGNAL ent3:bit:='0';
SIGNAL ent4:bit:='0';
SIGNAL ent5:bit:='0';
SIGNAL sal1:bit;
SIGNAL sal2:bit;
SIGNAL sal3:bit;
SIGNAL sal4:bit;
BEGIN
ckt1:cir3
PORT MAP
(
A=> ent1,
B=> ent2,
C=> ent3,
D=> ent4,
cont=> ent5,
w=> sal1,
x=> sal2,
y=> sal3,
z=> sal4
);
PROCESS

BEGIN
WAIT FOR 20 ns;
ent5 <='1';
WAIT FOR 20 ns;
ent5 <='0';
ent4 <='1';
wait for 20 ns;
ent5 <='1';
wait for 20 ns;
ent5 <='0';
ent4 <='0';
ent3 <='1';
wait for 20 ns;
ent5 <='1';
wait for 20 ns;
ent5 <='0';
ent4 <='1';
wait for 20 ns;
ent5 <='1';
wait for 20 ns;
ent5 <='0';
ent4 <='0';
ent3 <='0';
ent2 <='1';
wait for 20 ns;
ent5 <='1';
wait for 20 ns;
ent5 <='0';
ent4 <='1';
wait for 20 ns;
ent5 <='1';
wait for 20 ns;
ent5 <='0';
ent4 <='0';
ent3 <='1';

wait for 20 ns;

ent5 <='1';
wait for 20 ns;
ent5 <='0';
ent4 <='1';
wait for 20 ns;
ent5 <='1';
wait for 20 ns;
ent5 <='0';
ent4 <='0';
ent3 <='0';
ent2 <='0';
ent1 <='1';
wait for 20 ns;
ent5 <='1';
wait for 20 ns;
ent5 <='0';
ent4 <='1';
wait for 20 ns;
ent5 <='1';
END PROCESS;
END ARCHITECTURE arch_3;
TEST SOLO 0
ENTITY tb1_cir3 IS
END tb1_cir3;
ARCHITECTURE arch_3 OF tb1_cir3 IS
COMPONENT cir3 IS
PORT(
A,B,C,D,cont :IN BIT;
w,x,y,z :OUT BIT);
END COMPONENT cir3;

SIGNAL ent1:bit:='0';
SIGNAL ent2:bit:='0';
SIGNAL ent3:bit:='0';
SIGNAL ent4:bit:='0';
SIGNAL ent5:bit:='0';
SIGNAL sal1:bit;
SIGNAL sal2:bit;
SIGNAL sal3:bit;
SIGNAL sal4:bit;
BEGIN
ckt1:cir3
PORT MAP
(
A=> ent1,
B=> ent2,
C=> ent3,
D=> ent4,
cont=> ent5,
w=> sal1,
x=> sal2,
y=> sal3,
z=> sal4
);
PROCESS
BEGIN
WAIT FOR 20 ns;
ent4 <='1';
wait for 20 ns;
ent4 <='0';
ent3 <='1';
wait for 20 ns;

ent4 <='1';
wait for 20 ns;
ent4 <='0';
ent3 <='0';
ent2 <='1';
wait for 20 ns;
ent4 <='1';
wait for 20 ns;
ent4 <='0';
ent3 <='1';
wait for 20 ns;
ent4 <='1';
wait for 20 ns;
ent4 <='0';
ent3 <='0';
ent2 <='0';
ent1 <='1';
wait for 20 ns;
ent4 <='1';
END PROCESS;
END ARCHITECTURE arch_3;