Digital Electronics

Basic waveforms

A. Complete the waverforms for the circuits shown below:

1)

D2

D3

Q1

Q2

Q3
2)
3)
4)
5)

6)
B. For the following circuits described in VHDL, assume all signals that are not declared within the
architecture are ports of STD_LOGIC type. Suponiendo que todas las señales que aparecen y no
están ya declaradas dentro de la arquitectura son puertos del tipo STD_LOGIC, se pide:
a) Describe the entity of the circuit
b) Complete the sensitivity list of the process
c) Complete the simulation waveform

1)

ARCHITECTURE est OF a IS
SIGNAL d: STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN

PROCESS( )
BEGIN
IF p = '0' THEN
q <= d;
ELSIF clk'EVENT AND clk = '1' THEN
IF a = ‘1’ THEN
IF b = ‘1’ THEN
q <= d(0) & d(2 downto 1);
ELSE
q(1) <= ‘1’;
END IF;
ELSE
q <= d;
END IF;
END IF;
END PROCESS;

d <= “000” WHEN b = ‘1’ ELSE “001”;

END est;
2)

ARCHITECTURE una OF cim402 IS

SIGNAL p, q: std_logic;
BEGIN

PROCESS( )
BEGIN
IF a = '0' THEN
p <= '0';
q <= '1';
ELSIF clk'EVENT AND clk = '1' THEN
IF b = '1' then
p <= q;
q <= p;
ELSE
p <= NOT p;
END IF;
END IF;
END PROCESS;

c <= '1' WHEN p = q ELSE '0';

END una;
3)

ARCHITECTURE est OF c402 IS

SIGNAL p, q: std_logic;
BEGIN

PROCESS( )
BEGIN
IF a = '0' THEN
p <= '0';
q <= '1';
ELSIF clk'EVENT AND clk = '1' THEN
IF b = '1' then
p <= q;
ELSE
q <= NOT q;
END IF;
END IF;
END PROCESS;

c <= '1' WHEN p = q ELSE '0';

END est;