Task :3 Design and Implementation of Combinational Circuits

Aim:

To design and implement the complex combinational circuit

Software Details:
For design Functional Simulation: Modelsim
For design Synthesis: Quartus II
For design Implementation: Quartus II

Hardware Details:
Family: Cyclone IV
Device: EP4C
Package: FBGA
Pin count: 780

1. Circuit-1
RTL Code

module fa(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
assign sum=(a^b)^c;
assign carry=(a&b)|(b&c)|(c&a);
endmodule

module mux41(s0,s1,i0,i1,i2,i3,y);
input s0,s1,i0,i1,i2,i3;
output y;
assign y=s0?(s1?i0:i1):(s1?i2:i3);
endmodule

module task3(a1,b1,c1,a2,b2,c2,s0,s1,y);
input a1,b1,c1,a2,b2,c2,s0,s1;
output y;
wire c01,sum1,c02,sum2,y;
fa f1(.a(a1),.b(b1),.c(c1),.sum(sum1),.carry(c01));
fa f2(.a(a2),.b(b2),.c(c2),.sum(sum2),.carry(c02));
mux41 m1(.s0(s0),.s1(s1),.i0(c01),.i1(sum1),.i2(c02),.i3(sum2),.y(y));
endmodule
Test Bench Code

module testbench();
reg a1,b1,c1,a2,b2,c2,s0,s1;
wire y;
task3 t3(a1,b1,c1,a2,b2,c2,s0,s1,y);
initial
begin
a1 = 1'b0; b1 = 1'b0; c1 = 1'b1;
a2 = 1'b0; b2 = 1'b1; c2 = 1'b0;
s0 = 1'b0; s1 = 1'b0;

#20 a1 = 1'b0; b1 = 1'b1; c1 = 1'b1;

a2 = 1'b1; b2 = 1'b1; c2 = 1'b0;
s0 = 1'b0; s1 = 1'b1;

#20 a1 = 1'b0; b1 = 1'b0; c1 = 1'b0;

a2 = 1'b1; b2 = 1'b0; c2 = 1'b1;
s0 = 1'b0; s1 = 1'b1;

#20 a1 = 1'b1; b1 = 1'b0; c1 = 1'b1;

a2 = 1'b0; b2 = 1'b1; c2 = 1'b0;
s0 = 1'b1; s1 = 1'b0;

#20 a1 = 1'b0; b1 = 1'b1; c1 = 1'b1;

a2 = 1'b1; b2 = 1'b1; c2 = 1'b0;
s0 = 1'b1; s1 = 1'b1;

#20 a1 = 1'b1; b1 = 1'b1; c1 = 1'b0;

a2 = 1'b0; b2 = 1'b1; c2 = 1'b1;
s0 = 1'b0; s1 = 1'b1;
end
endmodule
Simulation Waveform
RTL Schematic

Implementation

Input: a1 = 1'b0; b1 = 1'b1; c1 = 1'b0; a2 = 1'b0; b2 = 1'b1; c2 = 1'b0; s0 = 1'b1; s1 = 1'b0;

Output: y = 1;
Inference:

The given Task 3 schematic has been implemented as Verilog code in Altera Quartus II
and implemented in the Altera Cyclone 2 4E FPGA kit. The test bench for the same circuit is
implemented in Verilog using Altera Modelsim.