Name : Qadeer Khan RollNo :2017-EE-149

Lab-4

OBJECT:-
Intro to dataflow Modeling.

TASK#01(a):-
To design and implement AND gate in Verilog using dataflow modeling.

CIRCUIT DIAGRAM:-

TRUTH TABLE:-

CODING:-
//Design Module
module gate(c,a,b);
input a,b;
output c;
assign c=a&b;
endmodule

//Stimulus Module
module xyz;

SIR SYED UNIVERSITY OF ENGG. AND TECNOLOGY 1

reg a,b;
wire c;
gate g1(c,a,b);
initial
begin
a=1’b0;
b=1’b0;
#20
a=1’b0;
b=1’b1;
#20
a=1’b1;
b=1’b0;
#20
a=1’b1;
b=1’b1;
#20
$finish;
end
endmodule

RESULT:-

TASK#01(b):-
To design and implement OR gate in Verilog using dataflow modeling.

CIRCUIT DIAGRAM:-

SIR SYED UNIVERSITY OF ENGG. AND TECNOLOGY 2

TRUTH TABLE:-

CODING:-
//Design Module
module gate(z,x,y);
input x,y;
output z;
assign z=x|y;
endmodule

//Stimulus Module
module pqr;
reg x,y;
wire z;
gate g1(z,x,y);
initial
begin
x=1'b0;
y=1'b0;
#20
x=1'b0;
y=1'b1;
#20
x=1'b1;
y=1'b0;
#20
x=1'b1;
y=1'b1;
#20
$finish;
end

SIR SYED UNIVERSITY OF ENGG. AND TECNOLOGY 3

endmodule

RESULT:-

TASK#01(c):-
To design and implement NAND gate in Verilog using dataflow modeling.
CIRCUIT DIAGRAM:-

TRUTH TABLE:-

CODING:-
//Design Module
module gate(c,a,b);
input a,b;
output c;
assign c=~(a&b);
endmodule

//Stimulus Module
module Qadeer;
reg a,b;
wire c;
gate g1(c,a,b);

SIR SYED UNIVERSITY OF ENGG. AND TECNOLOGY 4

initial
begin
a=1'b0;
b=1'b0;
#20
a=1'b0;
b=1'b1;
#20
a=1'b1;
b=1'b0;
#20
a=1'b1;
b=1'b1;
#20
$finish;
end
endmodule

RESULT:-

TASK#01(d):-
To design and implement NOR gate in Verilog using dataflow modeling.

CIRCUIT DIAGRAM:-

TRUTH TABLE:-

SIR SYED UNIVERSITY OF ENGG. AND TECNOLOGY 5

CODING:-
//Design Module
module gate(z,x,y);
input x,y;
output z;
assign z=~(x|y);
endmodule

//Stimulus Module
module savita;
reg x,y;
wire z;
gate g1(z,x,y);
initial
begin
x=1'b0;
y=1'b0;
#20
x=1'b0;
y=1'b1;
#20
x=1'b1;
y=1'b0;
#20
x=1'b1;
y=1'b1;
#20
$finish;
end
endmodule

RESULT:-
SIR SYED UNIVERSITY OF ENGG. AND TECNOLOGY 6
TASK#01(e):-
To design and implement NOT gate in Verilog using dataflow modeling.
CIRCUIT DIAGRAM:-

TRUTH TABLE:-

CODING:-
//Design Module
module gate(out,x);
input x;
output out;
assign out=~x;
endmodule

//Stimulus Module
module mallu;
reg x;
wire out;
gate g1(out,x);
initial
begin
x=1'b0;
#20
x=1'b1;

SIR SYED UNIVERSITY OF ENGG. AND TECNOLOGY 7

#20
$finish;
end
endmodule

RESULT:-

TASK#01(f):-
To design and implement XOR gate in Verilog using dataflow modeling.
CIRCUIT DIAGRAM:-

TRUTH TABLE:-

CODING:-
//Design Module
module gate(r,p,q);
input p,q;
output r;
assign r=p^q;
endmodule

//Stimulus Module
module ikmkb;

SIR SYED UNIVERSITY OF ENGG. AND TECNOLOGY 8

reg p,q;
wire r;
gate g1(r,p,q);
initial
begin
p=1'b0;
q=1'b0;
#20
p=1'b0;
q=1'b1;
#20
p=1'b1;
q=1'b0;
#20
p=1'b1;
q=1'b1;
#20
$finish;
end
endmodule

RESULT:-

TASK#02:-
To design D Flip Flop.
CIRCUIT DIAGRAM:-

SIR SYED UNIVERSITY OF ENGG. AND TECNOLOGY 9

TRUTH TABLE:-
CLK D Q Q’
0 0 1 0
1 0 0 1
0 1 0 1
1 1 1 0

CODING:-
//Design Module
module dff(q,qb,d,clk);
input d,clk;
output q,qb;
wire a,b,dbar;
assign dbar=~d;
assign a=~(d&clk);
assign b=~(dbar&clk);
assign q=~(a&qb);
assign qb=~(b&q);
endmodule

//Stimulus Module
module japan;

SIR SYED UNIVERSITY OF ENGG. AND TECNOLOGY 10

reg d,clk;
wire q,qb;
dff ff(q,qb,d,clk);
initial
begin
d=1'b0;
clk=1'b0;
#20
d=1'b0;
clk=1'b1;
#20
d=1'b1;
clk=1'b0;
#20
d=1'b1;
clk=1'b1;
#20
$finish;
end
endmodule

RESULT:-

TASK#03:-
To design 1 Bit Full Adder.
CIRCUIT DIAGRAM:-

SIR SYED UNIVERSITY OF ENGG. AND TECNOLOGY 11

TRUTH TABLE:-
Cin a b Cout Sum
0 0 0 0 0
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

EQUATIONS:-
Sum=a.b.Cin+a’.b.Cin+a.b’.Cin’
Cout=a.b+b.Cin+a.Cin
CODING:-
//Design Module
module obfa(sum,Cout,a,b,Cin);
input a,b,Cin;
output sum,Cout;
assign sum=(a&b&Cin)|((~a)&b&(~Cin))|(a&(~b)&(~Cin))|((~a)&(~b)&Cin);
assign Cout=(a&b)|(b&Cin)|(a&Cin);
endmodule

//Stimulus Module
module sir;
reg a,b,Cin;
wire sum,Cout;
obfa fa(sum,Cout,a,b,Cin);
initial
begin
a=1'b0;
b=1'b0;
Cin=1'b0;
#20
a=1'b0;
b=1'b1;

SIR SYED UNIVERSITY OF ENGG. AND TECNOLOGY 12

Cin=1'b1;
#20
a=1'b1;
b=1'b0;
Cin=1'b1;
#20
a=1'b1;
b=1'b1;
Cin=1'b1;
#20
$finish;
end
endmodule
RESULT:-

TASK#04:-
To design Master Slave JK Flip Flop.
CIRCUIT DIAGRAM:-

TRUTH TABLE:-
J k Clk clr q qb
0 0 0 0 0 1

SIR SYED UNIVERSITY OF ENGG. AND TECNOLOGY 13

 0 1 1 1 0 1
1 0 0 1 0 1
1 1 1 1 0 1

CODING:-
//Design Module
module MSJKFF(q,qb,j,k,clr,clk);
input j,k,clr,clk;
output q,qb;
wire a,b,c,x,y,z,clkb;
assign a=~(j&clr&clk&qb);
assign b=~(a&y);
assign c=~(b&clkb);
assign q=~(c&qb);
assign x=~(clk&k&q); j=1'b0;
assign y=~(x&b&clr); k=1'b1;
assign z=~(y&clkb); clr=1'b1;
assign qb=~(z&q&clr); clk=1'b1;
assign clkb=~clk; #30
endmodule j=1'b1;
k=1'b0;
//Stimulus Module clk=1'b0;
module bhutto; clr=1'b1;
reg j,k,clr,clk; #30
wire q,qb; j=1'b1;
MSJKFF ff(q,qb,j,k,clk,clr); k=1'b1;
initial clr=1'b1;
begin clk=1'b1;
j=1'b0; #30
k=1'b0; $finish;
clr=1'b0; end
clk=1'b0; endmodule
#30

SIR SYED UNIVERSITY OF ENGG. AND TECNOLOGY 14

RESULT:-

SIR SYED UNIVERSITY OF ENGG. AND TECNOLOGY 15