Assignment 7

Name:Saurav Kumar Roll no.:23UCC597

Q1) (i)D flip-

flop
a)Design code
module D_flipflop(
input clk,
input d,
output reg q
);
always@(posedge clk)
begin
q=d;
end
endmodule

b)Testbench
module D_testbench(

);
reg clk;
reg d;
wire q;
D_flipflop dut(.clk(clk),.d(d),.q(q));
integer i;
initial begin
for(i=0;i<8;i=i+1)
begin
{d,clk}=i;
#10;
end
$finish;
end
endmodule

c)Waveform

d)Schematic
(ii)JK flip flop
a)Design code
module JK_flipflop(
input clk,
input j,
input k,
output reg q
);
always@(posedge clk)
begin
if(j==0 & k==0)
q=q;
else if(j==0 & k==1)
q=0;
else if(j==1 & k==0)
q=1;
else if(j==1 & k==1)
q=-q;
end
endmodule

b)Testbench
module JK_testbench (

);
reg clk,j,k;
wire q;
JK_flipflop dut(.clk(clk),.j(j),.k(k),.q(q));
initial clk=0;
always #5 clk=-clk;
integer i;
initial begin
for(i=0;i<4;i=i+1)
begin
{j,k}=i;
#10;
end
$finish;
end
endmodule

c)Waveform
d)Schematic
Q2)(i)Design
code
module mod8_counter(
input clk,
input reset,
output reg [2:0] count
);
always @(posedge clk or posedge reset)
begin
if (reset)
count &lt;= 3’b000;
else if (count == 3’b111)
count&lt;= 3’b000;

else
count &lt;= count + 1;
end
endmodule

(ii)Testbench
module mod8_counter_tb;
reg clk;
reg reset;
wire [2:0] count;
mod8_counter uut
(
.clk(clk),
.reset(reset),
.count(count)
);
always #5 clk = ~clk;
initial begin clk = 0;
reset = 1;
#10
reset = 0;
#100
$finish;
end
always @(posedge clk) begin
$display(“Time=%0t, Count=%b”, $time, count);
end
endmodule
(iii)Waveform
(iv)schematic