ROLL NO : 420132

Redg no : 9201120
Dld assignment

D flip flop synchronous

Verilog code:

module d_flipflop_syncronous_clear(d, clk, clear, q, qbar);

input d,clk,clear;
output reg q, qbar;
always@(posedge clk)
begin
if(clear == 1)
begin
q<=0;
qbar<=1;
end
else
begin
q<=d;
qbar<=!d;
end
end
endmodule

Test bench:

module d_flipflop_syncronous_cleartest;

// Inputs
reg d;
reg clk;
reg clear;

// Outputs
wire q;
wire qbar;

// Instantiate the Unit Under Test (UUT)

d_flipflop_syncronous_clear uut (
.d(d),
.clk(clk),
.clear(clear),
.q(q),
.qbar(qbar)
 );

initial begin
// Initialize Inputs
clk = 0;
forever #20 clk=~clk;
end

initial begin
d=0;
clear=0;
#50;
d=1;
clear=0;
#50;
d=0;
clear=1;
#50;
d=1;
clear=1;
#50;
end
endmodule

RTL Schematic :
Simulation :

D flip flop asynchronous

Verilog code :

module d_flipflop_asyncronous(d, clk, clear, q, qbar);

input d,clk,clear;
output reg q, qbar;
always@(posedge clk or posedge clear)
begin
if(clear == 1)
begin
q<=0;
qbar<=1;
end
else
begin
q<=d;
qbar<=!d;
end
end
endmodule

Test bench :

module d_flipflop_asyncronoustest;

// Inputs
reg d;
reg clk;
reg clear;

// Outputs
wire q;
wire qbar;

// Instantiate the Unit Under Test (UUT)

d_flipflop_asyncronous uut (
.d(d),
.clk(clk),
.clear(clear),
.q(q),
.qbar(qbar)
);

initial begin
// Initialize Inputs
clk = 0;
forever #20 clk=~clk;
end

initial begin
d=0;
clear=0;
#50;
d=1;
clear=0;
#50;
d=0;
clear=1;
#50;
d=1;
clear=1;
#50;
 end

endmodule

RTL Schematic :

Simulation :
D flip flop Gate level modelling

Verilog code :

module d_flipflop_structural(q, qbar, d, clk);

input d, clk;
output q, qbar;
wire dbar, w1, w2;
not g1(dbar, d);
nand g2(w1, clk, d);
nand g3(w2, clk, dbar);
nand g4(q, qbar, w2);
nand g5(qbar, q, w1);

endmodule

Test bench :

module d_flipflop_structuraltest;

// Inputs
reg d;
reg clk;

// Outputs
 wire q;
wire qbar;

// Instantiate the Unit Under Test (UUT)

d_flipflop_structural uut (
.q(q),
.qbar(qbar),
.d(d),
.clk(clk)
);

initial begin
// Initialize Inputs
// Initialize Inputs
clk = 0;
forever #20 clk=~clk;
end

initial begin
d=0;
#50;
d=1;
#50;
end

endmodule
RTL Schematic :

Simulation :
Behavioural modelling for T flip flop

Verilog code for synchronous :

module tflipflop_syncronous(t,clk,rst,q,qbar);
input t,clk,rst;
output qbar;
output reg q;
always@(posedge clk )
begin
if(rst)
q<=1'b0;
else if(t)
q<=~q;
end
assign qbar = ~q;
endmodule

Test bench :

module tflipflop_syncronoustest;

// Inputs
reg t;
reg clk;
reg rst;

// Outputs
wire q;
wire qbar;

// Instantiate the Unit Under Test (UUT)

tflipflop_syncronous uut (
.t(t),
.clk(clk),
.rst(rst),
.q(q),
.qbar(qbar)
);

initial begin
// Initialize Inputs
clk = 0;
forever #20 clk=~clk;
end

initial begin
t=0;
 rst=1;
#30;
rst=0;
t=1;
#30;
t=0;
#30;
t=1;
#30;t=0;
#30;t=1;
#30;t=0;
#100;t=0;
#100;t=1;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

end

endmodule

RTL Schematic :
Simulation :

Verilog code for Asynchronous t flip flop :

module tflipflop(t,clk,rst,q,qbar);
input t,clk,rst;
output qbar;
output reg q;
always@(posedge clk or posedge rst)
begin
if(rst)
q<=1'b0;
else if(t)
q<=~q;
end
assign qbar = ~q;
endmodule

Test bench:

module tflipfloptest;

// Inputs
reg t;
reg clk;
reg rst;

// Outputs
wire q;
 wire qbar;

// Instantiate the Unit Under Test (UUT)

tflipflop uut (
.t(t),
.clk(clk),
.rst(rst),
.q(q),
.qbar(qbar)
);

initial begin
// Initialize Inputs
clk = 0;
forever #50 clk=~clk;
end

initial begin
t=0;
rst=1;
#30;
rst=0;
t=1;
#30;
t=0;
#30;
t=1;
#30;t=0;
#30;t=1;
#30;t=0;
#100;t=0;
#100;t=1;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

end

endmodule
RTL Schematic :

SIMULATION :
SR flip flop using case statement

Verilog code :

module sr_flipflop_casestatement_method(s,r,clk,q,qbar);
input s,r,clk;
output reg q;
output qbar;
always@(posedge clk)
case({s,r})
2'b01: q=0;
2'b10: q=1;
//2'b11: q=z;
2'b00: q=q;
endcase
assign qbar=~q;

endmodule

Test bench :

module sr_flipflop_casestatement_methodtest;

// Inputs
reg s;
reg r;
reg clk;

// Outputs
wire q;
wire qbar;

// Instantiate the Unit Under Test (UUT)

sr_flipflop_casestatement_method uut (
.s(s),
.r(r),
.clk(clk),
.q(q),
.qbar(qbar)
);

initial begin
// Initialize Inputs
clk = 0;
forever #50 clk=~clk;
end
initial begin
s=1;
 r=0;
#50;
s=0;
r=0;
#50;
s=0;
r=1;
#50;
s=1;
r=0;
#50;
s=0;
r=0;
#50;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

end

endmodule

RTL Schematic :
Simulation :

SR flip flop using if-else statements

Verilog code:

module sr_flipflop_ifelse_method(s,r,clk,q,qbar);
input s,r,clk;
output reg q,qbar;
always @(posedge clk)
begin
if(s==1)
begin
q=1;
qbar=0;
end
else if(r==1)
begin
q=0;
qbar=1;
end
else if(s==0&r==0)
begin
q=q;
qbar=qbar;
end
end
endmodule

Test bench :

module sr_flipflop_ifelse_methodtest;

// Inputs
reg s;
reg r;
reg clk;

// Outputs
wire q;
wire qbar;

// Instantiate the Unit Under Test (UUT)

sr_flipflop_ifelse_method uut (
.s(s),
.r(r),
.clk(clk),
.q(q),
.qbar(qbar)
);

initial begin
// Initialize Inputs
clk = 0;
forever #50 clk=~clk;
end
initial begin
s=1;
r=0;
#50;
s=0;
r=0;
#50;
s=0;
r=1;
#50;
s=1;
r=0;
#50;
s=0;
r=0;
#50;
// Wait 100 ns for global reset to finish
#100;
 // Add stimulus here

end

endmodule

RTL Schematic :
Simulation :

JK flip flop using case statements

Verilog code :

module jkflipflop_casestatement_method(j,k,clk,q,qbar);
input j,k,clk;
output reg q;
output qbar;
always@(negedge clk)
case({j,k})
2'b01: q=0;
2'b10: q=1;
2'b11: q=~q;
2'b00: q=q;
endcase
assign qbar=~q;

endmodule

Test bench :

module jkflipflop_casestatement_methodtest;

// Inputs
reg j;
 reg k;
reg clk;

// Outputs
wire q;
wire qbar;

// Instantiate the Unit Under Test (UUT)

jkflipflop_casestatement_method uut (
.j(j),
.k(k),
.clk(clk),
.q(q),
.qbar(qbar)
);

initial begin
// Initialize Inputs
clk = 0;
forever #50 clk=~clk;
end
initial begin
j=1;
k=0;
#100;
j=0;k=0;
#100;
j=0;k=1;
#100;
j=1;k=0;
#100;
j=1;k=1;
#100;
j=0;k=0;
#100;
j=1;k=1;
#100 j=0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

end

endmodule
RTL Schematic :

Simulation :
JK flip flop using if-else statements

Verilog code :

module jkflipflop_ifelse_method(j,k,clk,q,qbar);
input j,k,clk;
output reg q,qbar;
always@(negedge clk)
begin
if(j==0&k==1)
begin
q=0;
qbar=1;
end
else if(j==1&k==0)
begin
q=1;
qbar=0;
end
else if(j==1&k==1)
begin
q=~q;
qbar=q;
end
else //(j==0&k==0)
begin
q=q;
qbar=~q;
end
end
endmodule

Test bench :

module jkflipflop_ifelse_methodtest;

// Inputs
reg j;
reg k;
reg clk;

// Outputs
wire q;
wire qbar;

// Instantiate the Unit Under Test (UUT)

 jkflipflop_ifelse_method uut (
.j(j),
.k(k),
.clk(clk),
.q(q),
.qbar(qbar)
);

initial begin
// Initialize Inputs
clk = 0;
forever #50 clk=~clk;
end
initial begin
j=1;
k=0;
#100;
j=0;k=0;
#100;
j=0;k=1;
#100;
j=1;k=0;
#100;
j=1;k=1;
#100;
j=0;k=0;
#100;
j=1;k=1;
#100 j=0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

end

endmodule

RTL Schematic :
Simulation :
Verilog code for up counters in behavioural modelling

Verilog code :

module up_counter(input clk, reset, output [3:0]counter);

reg [3:0]counter_up;
always@(posedge clk or posedge reset)
begin
if(reset)
counter_up<=4'd0;
else
counter_up<=counter_up+4'd1;
end
assign counter = counter_up;

endmodule

Test bench :

module up_countertest;

// Inputs
reg clk;
reg reset;

// Outputs
wire [3:0] counter;

// Instantiate the Unit Under Test (UUT)

up_counter uut (
.clk(clk),
.reset(reset),
.counter(counter)
);

initial begin
// Initialize Inputs
reset = 1;
clk = 0;
#100;
clk=1;
reset=0;
#100;
clk=0;
 reset=0;
#100;
clk=1;
reset=0;
#100;
clk=0;
reset=0;
#100;
clk=0;
reset=0;
#100;
clk=1;
reset=1;
// Wait 100 ns for global reset to finish
#100;

// Add stimulus here

end

endmodule

RTL Schematic :
Simulation :

Verilog code for down counters in behavioural modelling

Verilog code :

module down_counter(input clk, reset, output [3:0]counter);

reg [3:0]counter_down;
always@(posedge clk or posedge reset)
begin
if(reset)
counter_down<=4'hf;
else
counter_down<=counter_down-4'd1;
end
assign counter = counter_down;

endmodule

Test bench :

module down_countertest;

// Inputs
reg clk;
reg reset;
 // Outputs
wire [3:0] counter;

// Instantiate the Unit Under Test (UUT)

down_counter uut (
.clk(clk),
.reset(reset),
.counter(counter)
);

initial begin
// Initialize Inputs
reset = 1;
clk = 0;
#100;
clk=1;
reset=0;
#100;
clk=0;
reset=0;
#100;
clk=1;
reset=0;
#100;
clk=0;
reset=0;
#100;
clk=0;
reset=0;
#100;
clk=1;
reset=1;
// Wait 100 ns for global reset to finish
#100;

end

endmodule
RTL Schematic :

Simulation :