VERILOG CODE:

JK Master Slave flip-flop

module jkff(input j,k,clk,output reg q);
always@(clk)
begin
case({j,k})
0:q<=q;
1:q<=0;
2:q<=1;
3:q<=~q;
endcase
end
endmodule
module jkms(input j,k,clk,output q);
wire t1;
jkff master(.j(j),.k(k),.clk(clk),.q(t1));
jkff slave(.j(t1),.k(~t1),.clk(~clk),.q(q));
endmodule

TEST BENCH:
JK Master Slave flip-flop
module bench;
reg j;
reg k;
reg clk;
wire q;
jkms uut (
.j(j),
.k(k),
.clk(clk),
.q(q)
);
initial begin
j = 0;k = 0; #100;
j = 0;k = 1; #100;
j = 1;k = 0; #100;
j = 1;k = 1; #100;
j = 1;k = 1; #100;