Digital System Lab

Week ‐10
vhdl code for 4bit BCD up counter using jk flip‐flop:
‐‐ write the VHDL code for loadable negative edge triggered JK flip‐flop
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity JK_FF is
Port (reset,J,K,clK1,Load,Load_input : in STD_LOGIC;
q,qbar : out STD_LOGIC);
end JK_FF ;
architecture Behavioral of JK_FF is
begin
process(clK1,J,K,reset)
variable x:std_logic:='0';
begin
if (clK1' event and clK1='1') then
case reset is
when '1'=>
x:='0';
when '0'=> if (J='0' and K='0')then
x:=x;
elsif(J='0' and K='1') then
x:='0';
elsif (J='1' and K='0') then
x:='1';
elsif(J='1' and K='1')then
x:=not x;
end if;
when others=> null;
end case;
end if;
q<= x;
qbar<= not x;
end process;
end Behavioral;

‐‐write the VHDL code for synchronous BCD up/down counter using JK flipflops
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BCD_updown_counter is
Port (reset,clk1,Load : in STD_LOGIC;
Load_input : in std_logic_vector(3 downto 0);
Q: out std_logic_vector(3 downto 0));
end BCD_updown_counter;

architecture behavioural of BCD_updown_counter is

component JK_FF is
Port (reset,J,K,clK1,Load,Load_input : in STD_LOGIC;
q,qbar : out STD_LOGIC);
end component;
signal temp : std_logic_vector(3 downto 0) := "0000";
signal k,l,m,r:std_logic;
begin
r<=(not temp(3)) and temp(0);
k<=temp(0);
l<=temp(0) and temp(1);
m<=temp(0) and temp(1) and temp(2);
d0 : JK_FF
port map (
reset => reset,
clk1 => clk1,
J => '1',
K => '1',
q => temp(0) ,
Load => Load ,
Load_input => Load_input(0)
);

d1 :JK_FF
port map (
reset => reset,
clk1 => clk1,
J => r,
K => k,
q => temp(1) ,
Load => Load ,
Load_input => Load_input(1)
);

d2 : JK_FF
port map (
reset => reset,
clk1 => clk1,
J => l,
K => l,
q => temp(2),
Load => Load ,
Load_input => Load_input(2)
);

d3 : JK_FF
port map (
reset => reset,
clk1 => clk1,
J => m,
K => k,
q => temp(3),
Load => Load ,
Load_input => Load_input(3)
);

Q(3) <= temp(3);

Q(2) <= temp(2);
Q(1) <= temp(1);
Q(0) <= temp(0);
end behavioural;

Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY BCD_updown_counter_tb IS
END BCD_updown_counter_tb;

ARCHITECTURE behavior OF BCD_updown_counter_tb IS

COMPONENT BCD_updown_counter
PORT(
clk1 : IN std_logic;
reset : IN std_logic;
Load : in STD_LOGIC;
Load_input : in std_logic_vector(3 downto 0) ;
Q : out std_logic_vector(3 downto 0)
);
END COMPONENT;

‐‐Inputs
SIGNAL clk1 : std_logic := '0';
SIGNAL reset : std_logic := '0';
SIGNAL load : std_logic := '0';
SIGNAL Q : std_logic_vector(3 downto 0);
SIGNAL Load_input : std_logic_vector(3 downto 0);
BEGIN
uut: BCD_updown_counter PORT MAP(
clk1 => clk1,
reset => reset,
Load => Load,
Load_input => Load_input,
Q => Q
);

clock_process :process
begin
clk1 <= '0';
wait for 10 ns;
clk1 <= '1';
wait for 10 ns;
end process;

‐‐ Stimulus process
stim_proc: process
begin
‐‐ hold reset state for 100 ns.
reset <= '1';
wait for 20 ns;
reset <= '0';
wait for 20 ns;
load <= '1';
wait for 20 ns;
Load_input(0) <= '0';
Load_input(1) <= '0';
Load_input(2) <= '0';
Load_input(3) <= '0';
 wait for 20 ns;
load <= '0';
wait for 20 ns;
load <= '1';
wait for 20 ns;
Load_input(0) <= '0';
Load_input(1) <= '0';
Load_input(2) <= '0';
Load_input(3) <= '1';
wait for 20 ns;
load <= '0';
wait for 20 ns;
load <= '1';
wait for 20 ns;
Load_input(0) <= '0';
Load_input(1) <= '0';
Load_input(2) <= '1';
Load_input(3) <= '0';
wait for 20 ns;
load <= '0';
wait for 20 ns;
load <= '1';
wait for 20 ns;
Load_input(0) <= '0';
Load_input(1) <= '0';
Load_input(2) <= '1';
Load_input(3) <= '1';
wait for 20 ns;
load <= '0';
wait for 20 ns;
load <= '1';
wait for 20 ns;
Load_input(0) <= '0';
Load_input(1) <= '1';
Load_input(2) <= '0';
Load_input(3) <= '0';
wait;
end process;
end;