Logic Synthesis

Timing Optimization

Courtesy RK Brayton (UCB) 1

and A Kuehlmann (Cadence)
Restructuring for Timing Optimization
Outline:
• Definitions and problem statement
• Overview of techniques (motivated by adders)
– Tree height reduction (THR)
– Generalized bypass transform (GBX)
– Generalized select transform (GST)
– Partial collapsing

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Timing Optimization

Factors determining delay of circuit:

• Underlying circuit technology
– Circuit type (e.g. domino, static CMOS, etc.)
– Gate type
– Gate size
• Logical structure of circuit
– Length of computation paths
– False paths
– Buffering
• Parasitics
– Wire loads
– Layout
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Problem Statement
Given:
• Initial circuit function description
• Library of primitive functions
• Performance constraints (arrival/required times)
Generate:
an implementation of the circuit using the primitive functions, such
that:
– performance constraints are met
– circuit area is minimized

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 Current Design Process
Behavioral description
Behavior
Optimization
(scheduling)
Logic and latches
Partitioning
(retiming)
Logic equations
Logic synthesis
•Technology independent
•Gate library •Technology mapping
•Perf. Constraints Gate netlist
•Delay models
Timing driven
place and route
Layout 5
Technology Mapping for Delay

Function
tree

Buffer
tree

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Overview of Solutions for Delay
• Circuit re-structuring
– Rescheduling operations to reduce time of computation
• Implementation of function trees (technology mapping)
– Selection of gates from library
• Minimum delay (load independent model - Kukimoto)
• Minimize delay and area (Jongeneel, DAC’00)
(combines Lehman-Watanabe and Kukimoto)
• Implementation of buffer trees
– Touati (LT-trees)
– Singh
• Resizing

• Constant delay synthesis

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Circuit Restructuring

Approaches:
Local:
• Mimic optimization techniques in adders
– Carry lookahead (THR tree height reduction)
– Conditional sum (GST transformation)
– Carry bypass (GBX transformation)
Global:
• Reduce depth of entire circuit
– Partial collapsing
– Boolean simplification

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Restructuring Methods
Performance measured by
• levels,
• sensitizable paths,
• technology dependent delays
• Level based optimizations:
– Tree height reduction (Singh ‘88)
– Partial collapsing and simplification (Touati ‘91)
– Generalized select transform (Berman ‘90)
• Sensitizable paths
– Generalized bypass transform (McGeer ‘91)

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Tree-Height Reduction (THR)
Singh’88:

6 Collapsed 5
n Critical Critical region
5 5 Duplicated
region n’ logic
l m 1 m
1 1 1
4 k 1 2 4 k
i j 0 0
3 i j
3
h h

0 0 0 0 2 0 0 0 0
0 0 0 2 0
a b c d e f g a b c d e f g

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 Tree-Height Reduction

4 New delay = 5
n’
3
Collapsed 5 5
Critical region 2
Duplicated
n’ logic 1
m m
1 1 1 1
1 2 4 k 1 2 4
0 0 0 k
i j i j
3 3
0
h h

0 0 0 0 2 0 0 0 0 0 0 2 0 0
a b c d e f g a b c d e f g

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Generalized bypass transform (GBX)
McGeer’91: • Make critical path false
– Speed up the circuit
• Bypass logic of critical path(s)

fm=f fm+1 … fn=g

fm =f fm+1 … fn=g 0
g’
1

Boolean dg s-a-0 redundant

difference __
12
df
 GBX and KMS transform

GBX gives little area increase, BUT creates an untestable fault

(on control input to multiplexer)

KMS transform: (remove false paths without increasing delay)

• fk is last node on false path that fans out.
• Duplicate false path {f1,…, fk} -> {f’1, … , f’k}
• f’j fans out to every fanout of fj except fj+1, and fj just fans out to fj+1
• Set f0 input to f1 to controlling value and propagate constant (can
do because path is false and does not fanout)
KMS results
– Function of every node, except f1, … ,fk is unchanged
– Added k nodes
– Area added in linear in size of length of false paths; in practice
small area increase.
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KMS
Keutzer, Malik, Saldanha’90:

fm+1 fm+2 fm+k fm+k+1 … fn

Delay is not
f’m+1 f’m+2 … f’m+k increased

0 fm+1 fm+2 fm+k fm+k+1 … fn

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 Generalized select transform (GST)
Berman’90: Late signal feeds multiplexor
a out
b
c d e f g

a=0
b 0
out
c d e f g
a=1
1
b

c d e f g a 15
 a c
g
h
GST vs GBX
… 0
g’
b 1
a GBX
dh a c
GBX g
__
da … 0 h
g’
b 1
Note: a
Boolean a=0
difference = b
c d e f g
h a=1
 ha  h a b
a
c d e f g

a=0
b 0 out
GST
a=1 c d e f g 1
b
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c d e f g a
GST vs GBX
• Select transform appears to be more area efficient
• But Boolean difference generally more efficiently formed in
practice
• No delay/speedup advantage for either transform
• Can reuse parts of the critical paths for multiple fanouts on GST

0 out2
GST
1

a=0 0 out1
b c d e f g 1
a=1
b c d e f g a

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Technology Independent Delay Reductions

Generally THR, GBX, GST (critical path based methods) work OK,
– but very greedy and computationally expensive

Why are technology independent delay reductions hard?

Lack of fast and accurate delay models
b s – # levels, fast but crude
e l – # levels + correction term (fanout, wires,… ): a little better,
t o but still crude (what coefficients to use?)
t w – Technology mapped: reasonable, but very slow
e e
r – Place and route: better but extremely slow
r
– Silicon: best, but infeasibly slow (except for FPGAs)

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Conclusions
• Variety of methods for delay optimization
– No single technique dominates
– When applied to ripple-carry adder get
– Carry-lookahead adder (THR)
– Carry-bypass adder (GBX)
– Carry-select adder (GST)
– Clustering/Partial collapse
• All techniques ignore false paths when assessing the delay and
critical regions
– Can use KMS transform to eliminate false paths without
increasing delay (Caveat: potentially large increase in area)

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