Advanced VLSI Design

Dr. Premananda B.S.

BITS Pilani
Pilani Campus
 BITS Pilani
Pilani Campus

MEL ZG623, Advanced VLSI Design

Lecture No. 12
Agenda

• Introduction/Review, Design issues

• Sequential logic circuit
• Dynamic latches and Registers
• Timing issues in clock systems
• Clock generation and distribution
• Asynchronous system design
• Interfacing circuits

BITS Pilani, Pilani Campus

Reference Books
• Jan M. Rabaey and A. Chandrakasan, “Digital Integrated
Circuits”, 2nd Edition, Prentice Hall Electronics and VLSI
Series.
• Ming-Bo Lin, “Introduction to VLSI systems A logic circuit
and system perspective”, CRC press. Taylor & Francis
Group.
• Neil H. E. Weste, David Harris, and Ayan Banerjee, “CMOS
VLSI Design” 3rd/4th edition, Pearson education.
• John P. Uyemura, “Introduction to VLSI Circuits and
systems” Wiley.
• John P. Uyemura, CMOS Logic Circuit Design Kluwer
Academic Publishers.
• …
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Multipliers
• Array Multiplier
• Carry-save multiplier
• Baugh-Wooley Multiplier
• Tree Multiplier
• Booth Multiplier
Dot diagram for array multiplier
Tree multipliers

(a) array multiplier; (b) using 3:2 compressors; (c) using 4:2 compressors.
Wallace-Tree Multiplier
Wallace-Tree Multiplier
Booth Encoding
• Instead of 3Y, try –Y, then increment next partial product to
add 4Y
• Similarly, for 2Y, try –2Y + 4Y in next partial product
• Radix-4 modified Booth encoding values
Booth Multiplier: Example
Summary
• Tree Multiplier
• Booth Multiplier
Agenda Contd …

• Datapath subsystem design

• High speed computer arithmetic design
• Adders, Multipliers, Barrel shifter
• Logical efforts
• Optimizing logic circuits
• Wire design principles
• Deep submicron device engineering
• Scaling theory, geometrical/physical effects

BITS Pilani, Pilani Campus

Shifters
• Shifters are used to either scale-down or scale-up
operands or the results.
• The following scenarios give the necessity of a shifter:
– Performing the addition of N numbers each of n bits long, sum
can grow up to n+log2N bits long. If accumulator is of n bits long,
then an overflow error will occur, overcome by shifter to scale
down the operand by an amount of log2N.
– While calculating the product of two n bit numbers, the product
can grow up to 2n bits long. Lower n bits get neglected and sign
bit is shifted to save the sign of product.
– Addition of two floating-point numbers, one of operands has to
be shifted appropriately to make the exponents of two numbers
equal.
From the above cases it is clear that, a shifter is required in the
architecture of a Digital Signal Processor.
Barrel Shifters
• Single-cycle structure of a shifter is a combinational logic
circuit.
• A combinational logic circuits that can implement the
shifter with an arbitrary number of shifts is referred as
barrel shifters.
• Barrel shifters can be realized in either a linear or
logarithmic number of stages.
• The former will be denoted as a linear barrel shifter and
the latter as a logarithmic barrel shifter.
• A linear barrel shifter consists of an array of nMOS or TG
switches in which the number of rows equals the word
length of the data and the number of columns is equal to
the maximum amount of shift.
 Barrel Shifter
Block diagram of a Barrel shifter
Figure: Implementation of a 4-bit, shift-right barrel shifter
Premananda B S
4-bit Left-rotation Linear Barrel Shifter

• A 4-bit left-rotation linear barrel shifter is implemented by

an array of nMOS switches, with each column containing
four nMOS switches.
• Each column is controlled by si and circularly shifts left
the input of a number of i bit positions.
• Each stage shifts its input the number of 0 or i-bit
positions depending on the value of si (0 or 1).
• A linear barrel shifter can also be implemented with TG
switches.
4-bit Left-rotation Linear Barrel Shifter based on
nMOS Switches
4-bit Left/right-rotation Linear Barrel Shifter based on
TG-switches
Major features of barrel shifters with linear
number of stages
• The input signal has to pass through at most one nMOS
or TG switch.
• The layout size is not dominated by the active devices,
nMOS or TG switches, but instead by the number of
wires running through the module.
• The shift amount of the shifter is selected by individual
control signals si exclusively.
• Shift amount may in an encoded binary format.
– An n-to-2n decoder is needed to convert the input
binary format into the required 1-out-of-2n code.
Logarithmic Barrel Shifter

• A logarithmic barrel shifter consists of log2n

columns, with each containing n 2-to-1 multiplexers.
• The multiplexers may be constructed with nMOS or
TG switches.
• Each column shifts its input the number of 0 or 2i bit
positions depending on the value of si (0 or 1).
• The shift amount is represented as a binary code.
• The logarithmic barrel shifter is faster and consumes
less area than the linear barrel shifter for large n.
8-bit logical/arithmetic-left Logarithmic Barrel
Shifter
• The logarithmic barrel shifter is implemented by three
stage multiplexer columns, with each containing eight 2-
to-1 multiplexers.
• Each column of the multiplexers is controlled by si and
shifts the input a number of si × 2i bit positions.
• Each column shifts its input the number of 0 or 2i bit
positions, depending on the value of si (0 or 1).
8-bit logical/arithmetic-left Logarithmic Barrel Shifter
based on 2-to-1 multiplexers
Summary
• Linear barrel shifter
• Logarithmic barrel shifter
Agenda Contd …

• Wire design principles

• Datapath subsystem design
• High speed computer arithmetic design
• Adders, multipliers, barrel shifter

• Logical efforts
• Optimizing logic circuits
• Deep submicron device engineering
• Scaling theory, geometrical/physical effects

BITS Pilani, Pilani Campus

Logical Effort
• Introduction
• Logical Effort of Gates
• Delay in logic gate
• Branching effort
• Optimum Path Delay
• Transistor Sizing
• Examples
• Best number of stages
Logical Effort
• Each logic gate is characterized by two quantities:
logical effort and parasitic (& non-ideal) delay.
• Logical effort of a logic gate tells how much worse it is at
producing output current than is an inverter, given each
of its inputs may contain only same input capacitance as
the inverter.
• Logical effort describes drive capability relative to that of
a reference inverter.
• Logical effort is a function of topology, is independent of
the actual size of the logic gate, allowing.
• Logical effort, an easy way to estimate delay in an MOS
circuit.
Logical Effort Contd..
• Logical effort per input for a particular input is the ratio
of the capacitance of that input to the total input
capacitance of the reference inverter.
• Logical effort ‘g’ of any stage is defined as the ratio of
its input capacitance to that of an inverter (reference
gate) that delivers equal output current.
• We can find logical effort by scaling a logic cell to have
the same drive as a 1X minimum-size inverter.
• The logical effort, g, is the ratio of the input
capacitance, Cin, of the 1X logic cell to Cinv.
• Logical effort achieves an approximate optimum,
because it ignores a number of second-order effects.
 Logical Effort Contd..
• A design procedure for achieving the least delay along a
path of a logic network.
• By comparing delay estimates of different logic
structures, the fastest candidate can be selected.
• Logic effort allows us to compare alternative circuit
topologies.
• Logical effort is a method to make these decisions:
– Uses a simple model of delay
– Allows back-of-the-envelope calculations
• Design the logic gate, picking transistor sizes that make
it as good a driver of output current as the reference
inverter.
Delay in a Logic Gate
d abs
• Express delays in process-independent unit d 

• Delay has two components: d = f + p
• Thus, delay = logical effort x electrical effort + parasitic delay
• f: effort delay = gh
– has two components
• g: logical effort
– Measures relative ability of gate to deliver current
• h: electrical effort = Cout / Cin
– Ratio of output to input capacitance
– Sometimes called fanout
• p: parasitic delay
– Set by internal parasitic capacitance
Computing Logical Effort
• Logical effort is the ratio of the input capacitance of a gate
to the input capacitance of an inverter delivering the same
output current.

2 2 A 4
Y
2 B 4
A 2
A Y Y
1 B 2 1 1

Cin = 3 Cin = 4 Cin = 5

g = 3/3 g = 4/3 g = 5/3
Computing Logical Effort

2 2 A 4
Y
2 B 4
A 2
A Y Y
1 B 2 1 1

Cin = 3 Cin = 4 Cin = 5

g = 3/3 g = 4/3 g = 5/3
Logical Effort & Parasitic Delay of
Inverter, NAND & NOR
Naming of complex CMOS combinational
logic cells
Computing Logical Effort

• Draw the CMOS circuit for the following OAI and AOI
logic gates and compute logical effort.
Logical Effort and Logical Area
Multistage Logic Networks
• Logical effort generalizes to multistage networks
• Path Logical Effort G  gi
Cout  path
• Path Electrical Effort H
Cin  path
• Path Effort F   f i   gi hi

• F = GH
Paths that Branch
• Consider paths that branch:
15
90
G =1
5
H = 90 / 5 = 18
GH = 18 15
90
h1 = (15 +15) / 5 = 6
h2 = 90 / 15 = 6
F = g1g2h1h2 = 36 = 2GH
Branching Effort
• Introduce branching effort
– Accounts for branching between stages in path
Con path  Coff path
b
Con path
B   bi
Note:

 h  BHi

• Now we compute the path effort

– F = GBH
Multistage Logic Networks
Stage effort: fi = gihi
Path electrical effort: H = Cout/Cin
Path logical effort: G = g1g2…gN
Branching effort: B = b1b2…bN
Path effort: F = GHB
= f1f2…fN
THANK YOU

BITS Pilani, Pilani Campus