Bahria University, Lahore Campus

Department of Computer Sciences

Lab Journal 12
(Spring 2020)

Course: Digital Logic Design Lab Date:

Course Code: CEL-120 Max Marks: 30
Faculty’s Name: Ms. Munazza Sher Lab Engineer: Mr. Shoaib Khan

Name: _____________________________ Enroll No: _______________________

Objective(s):

 To construct a JK Flip Flop with basic logic gates.

Lab Tasks:

Task 1: Construct a JK Flip Flop using NAND gates and record its values in the table. Construct
the circuit on breadboard as well.
Task 2: Revision of Previous Flip-Flops & Viva Voce.

Lab Grading Sheet :

Max
Obtained
Task Mark Comments(if any)
Marks
s
1. 10
2. 10
3. 10

Total 30 Signature

Note : Attempt all tasks and get them checked by your Lab Instructor
 Lab 12: JK flip-flop

Objective(s):

“To construct and verify the characteristics of JK Flip-flop”.

Tool(s) used:

 KL-31001 DLD Trainer

 Module KL-33008
 Connector leads

Overview:

The J-K flip-flop is the most versatile of the basic flip-flops. If J and K are both low then no
change occurs. If J and K are both high at the clock edge then the output will toggle from one
state to the other. It can perform the functions of the set/reset flip-flop and has the advantage that
there are no ambiguous states.

Task 01+02: Time: 30 Minutes

Construct a JK flip-flop using NAND gates (Module KL-33008, block d). Construct the circuit
on breadboard as well.
 Task 03+04: Time: 30 Minutes

Record its values in the given table

CLK J K Q Q́

0 0 0 1 0

0 0 1 0 1

0 1 0 1 0

0 1 1 0 1

1 0 0 0 1

1 0 1 1 0

1 1 0 0 1

1 1 1 1 0