Bahria University, Lahore Campus

Department of Computer Sciences

Lab Journal 07
(Spring 2020)

Course: Digital Logic Design Lab Date:

Course Code: CEL-120 Max Marks: 30
Faculty’s Name: Ms. Munazza Sher Lab Engineer: Mr. Shoaib Khan

Name: _____________________________ Enroll No: _______________________

Objective(s):
▪ To construct half adder circuit.

Lab Tasks:

Task 1: Construct Half Adder with basic logic gates (using Module KL-33004, block a).

Task 2: Construct the given circuit and observe the output of each gate.

Lab Grading Sheet :

Max Obtained
Task Comments(if any)
Marks Marks
1. 15
2. 15

Total 30 Signature

Note : Attempt all tasks and get them checked by your Lab Instructor
 Lab 07: Half Adder Circuit

Objective(s):

“To construct half adder circuit”.

Tool(s) used:

● KL-31001 DLD Trainer

● Module KL-33004
● Connector leads

Overview:

The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C).
The carry signal represents an overflow into the next digit of a multi-digit addition.

Task 01: Time: 30 Minutes

Construct Half Adder with basic logic gates (using Module KL-33004, block a).

TruthTable:

Input Output

SW1 (A) SW0 (B) F1 F2

0 0 0 0

0 1 1 0

1 0 1 0
 1 1 0 1

Diagram:

Task 02: Time: 30 Minutes

Construct the given circuit and observe the output of each gate.
A B G1 G2 G3 G4 G5 G6 G7

0 0 1 1 1 1 0 1 0

0 1 1 0 0 1 1 1 0

1 0 0 1 1 0 1 1 0

1 1 0 0 1 1 0 0 1

0 0 1 1 1 1 0 1 0

0 1 1 0 0 1 1 1 0

1 0 0 1 1 0 1 1 0

1 1 0 0 1 1 0 0 1
Diagram: