(Total: 80 marks)

INSTRUCTION: Answer ALL questions.

Question 1

(a) Develop digital circuit for pneumatics Application of A+, B+, A-, B-

(15 marks)

(b) Construct the expected output waveform/timing diagram of the system

(5 marks)

UniKL CDDH v3 Appendix N(F) - Assessment Coversheet v1 (2020-04-23)

Question 2
(a) Establish two inputs Encoder circuits from basic combinational logic circuits, develop the
truth table and timing diagram.

UniKL CDDH v3 Appendix N(F) - Assessment Coversheet v1 (2020-04-23)

TRUTH TABLE

INPUT OUTPUT
SIGNAL 1 Y1 Y2 Y3 Y4
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0

(5 marks)
(b) Design two inputs and four outputs Decoder circuits using combinational logic, develop
the truth table and timing diagram.

UniKL CDDH v3 Appendix N(F) - Assessment Coversheet v1 (2020-04-23)

TRUTH TABLE

INPUT OUTPUT
Signal 1 Signal 2 Y1 Y2 Y3 Y4
0 0 0 1 1 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 0

(5 marks)

(c) Construct two inputs Multiplexer circuits from basic combinational logic circuits, develop
truth table and timing diagram.
(5 marks)
UniKL CDDH v3 Appendix N(F) - Assessment Coversheet v1 (2020-04-23)
TRUTH TABLE

UniKL CDDH v3 Appendix N(F) - Assessment Coversheet v1 (2020-04-23)

 DATA-SELECT INPUTS

S1 S0 INPUT SELECTED

0 0 D0

0 1 D1

1 0 D2

1 1 D3

(d) Develop two input and four outputs Demultiplexer circuits from basic combinational logic
circuits, develop the truth table and timing diagram.
(5 marks)

UniKL CDDH v3 Appendix N(F) - Assessment Coversheet v1 (2020-04-23)

TRUTH TABLE

UniKL CDDH v3 Appendix N(F) - Assessment Coversheet v1 (2020-04-23)

 I S0 S1 D0 D1 D2 D3

I 0 0 1 0 0 0

I 0 1 0 1 0 0

I 1 0 0 0 1 0

I 1 1 0 0 0 1

UniKL CDDH v3 Appendix N(F) - Assessment Coversheet v1 (2020-04-23)

Question 3

(a) Develop a single basic unit of memory and develop the truth table to read/write from the unit
cell.

TRUTH TABLE

(12 marks)

UniKL CDDH v3 Appendix N(F) - Assessment Coversheet v1 (2020-04-23)

(b) Design digital circuit for three bits SISO register and plot the timing diagram.

(4 marks)

UniKL CDDH v3 Appendix N(F) - Assessment Coversheet v1 (2020-04-23)

(c) Construct digital circuit for three bits PISO register and plot the timing diagram.
(4 marks)

UniKL CDDH v3 Appendix N(F) - Assessment Coversheet v1 (2020-04-23)

Question 4
(a) Construct three bits Johnson and ring counter digital circuits, develop the truth table, and
draw the timing diagram waveform.
. (8 marks)

TRUTH TABLE
CLOCK Q1 Q2 Q3

0 0 0 0

1 1 0 0

2 1 1 0

3 1 1 1

4 1 1 1

UniKL CDDH v3 Appendix N(F) - Assessment Coversheet v1 (2020-04-23)

(b) The operation of Apple Sorting System as in Figure 4 as follows:

Figure 4 Apple Station

Operation:

When PB1 (Start Push Button) is pressed, the box conveyor moves. Upon the detection of box
present, the box conveyor stop, and the Apple conveyor start. Part sensor will counter count for
6 apples. Apple conveyor stops and box conveyor start again. Counter will reset and operation
repeats until PB2 (STOP Push Button) is pressed.
(a) Design the digital electronics circuit of the system
(8 marks)

(b) Draw the timing diagram waveform.

UniKL CDDH v3 Appendix N(F) - Assessment Coversheet v1 (2020-04-23)
 (4
marks)

END OF FINAL ASSESMENT

UniKL CDDH v3 Appendix N(F) - Assessment Coversheet v1 (2020-04-23)