SOUTHERN UNIVERSITY COLLEGE

SEMESTER A

YEAR 2022

FINAL EXAMINATION

BALS3033 LOGIC SYSTEM DESIGN

DATE : 09 MAY 2022 DURATION : 2 HOURS 30 MINUTES

BACHELOR OF ENGINEERING (HONOURS) IN ELECTRONIC ENGINEERING

BACHELOR OF ELECTRONIC ENGINEERING WITH HONOURS

YEAR THREE

Instruction to Candidates :

1. Answer ALL questions. All questions carry equal marks.

2. All answers must be written on the answer sheet with pen.
3. Begin to answer each new question on a new page.
4. Programmable and Semi-Programmable Scientific Calculators are PROHIBITED to use.
5. Return the question paper together with your answer booklet.

This question paper consists of 4 questions on 5 printed pages.

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BALS3033 LOGIC SYSTEM DESIGN

Q1. (a)

Figure 1

(i) Write a Verilog HDL conditional signal assignment statement to

represent the circuit shown in Figure 1. Assume an inherent delay in the
circuit that causes the change in output to occur 15ns after a change in
input. (3 marks)

(ii) Write a Data Flow Verilog HDL code using an if-else statement to
represent the circuit shown in Figure 1. Assume that all delays are
negligible.
Notes: The module and ports declaration can be excluded. (8 marks)

(b) Write the Verilog HDL code of the decoder using the case statement,
concatenation operator, and continuous assignment. The 2 to 4 Binary
Decoder is shown in Figure 2. The relationship between the inputs and outputs
is illustrated in Table 1. (14 marks)

Inputs Outputs
EN A1 A2 D0 D1 D2 D3
1 X X 0 0 0 0
0 0 0 0 0 0 1
0 0 1 0 0 1 0
0 1 0 0 1 0 0
0 1 1 1 0 0 0

Figure 2 Table 1

[Total : 25 marks]

This question paper consists of 4 questions on 5 printed pages.

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BALS3033 LOGIC SYSTEM DESIGN

Q2. (a)

Figure 3

(i) Draw the circuit of the Verilog process shown in Figure 3. (6 marks)

(ii) Justify the reason of clr is used in the sensitivity list instead of C.
(2 marks)

(b) A client requests to design a chip for converting an 8-bit binary number to a 3
digit decimal number to be displayed on three 7 segment LEDs. Another input
signal, signednumber, is used to determine whether to interpret the binary
number as a signed or unsigned number. If signednumber is a 1, the binary
number is interpreted as a signed number, otherwise it is interpreted as an
unsigned number. An optional negative sign is displayed on a fourth 7 segment
LED as shown in Figure 4. The 7-segment BCD table as shown in Table 2. As
a design engineer, write the behavioral Verilog code for the design.

Sign Hundreth Tenth Unit

Figure 4
7-Segment BCD Decimal
1111110 0
0110000 1
1101101 2
1111001 3
0110011 4
1011011 5
1011111 6
1110000 7
1111111 8
1110011 9
0000001 -
Table 2
(17 marks)
[Total : 25 marks]

This question paper consists of 4 questions on 5 printed pages.

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BALS3033 LOGIC SYSTEM DESIGN

Q3. (a) Determine the state diagram for the Moore system whose output is 1 if and only
if the input shown in the Table 3 has been alternating for at least four clock
periods. (10 marks)

x 0 0 1 0 1 1 0 1 0 1 0 1 0 0
y ? ? 0 0 0 1 0 0 0 1 1 1 1 1 0
Table 3

(b) FSC Sdn Bhd is planning to develop a modulo-4 up/down counter chip using
D-flip-flop. The count is represented by the content of the flip-flop. The circuit
has a Count signal and an Up signal. The counter counts when Count is asserted,
and stops when Count is de-asserted. The Up signal determines the direction of
the count. When Up is asserted, the count increments by one at each clock cycle.
When Up is de-asserted, the count decrements by one at each clock cycle. The
Modulo-4 up/ down counter condition as shown in Table 4.

(i) Construct the Finite State table for the counter chip. (8 marks)

(ii) Determine the excitation equations of the counter chip. (4 marks)

(iii) Draw the circuit diagram of the counter chip. (3 marks)

Count Up Clock Status

0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Table 4
0 No Change
1 Stop Count
0 No Change
1 Stop Count
0 No Change
1 Count Down
0 No Change
1 Count Up

[Total : 25 marks]

This question paper consists of 4 questions on 5 printed pages.

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BALS3033 LOGIC SYSTEM DESIGN

Q4. Design a binary-to-BCD converter that converts a 10-bit binary number to a 3-digit
BCD number. Assume that the binary number is ≤ 999. Initially the binary number is
placed in Register B. When an St signal is received, conversion to BCD takes place and
the resulting BCD number is stored in the Register A (12 bits). Initially A contains 0000
0000 0000. The conversion algorithm is as follows:

1. If the digit in any decade of A is ≥ 0101, add 0011 to that decade.

2. The shift the A Register together with B Register one place to the left.
3. Repeat until 10 shifts have occurred.
4. At each step, as the left shift occurs, this effectively multiplies the BCD number by
2 and adds in the next bit of the binary number.

(a) Illustrate the algorithm by converting 10011101 to BCD. (3 marks)

(b) Develop the state diagram for the converter (Four states only).
(6 marks)

(c) Write a Verilog description for the converter. (16 marks)

[Total : 25 marks]

________________________________________

This question paper consists of 4 questions on 5 printed pages.