ECE 274a Fall 2022

Lab 2: Combinational logic design – Two-digit display

Lab objectives:
a) Use the combinational logic design process to design a combinational circuit – seven
segment decoder
b) Use the vector (multi-bit) signal syntax in Verilog
c) Write the testbench to validate the designed code before implementation
d) Continue using the BASYS3 board to implement the designed circuit

Pre-Lab 2 Assignment (20 pts) – Due Date: 11.59 pm Tuesday September 13, 2022
• Create the truth table and derive the optimized/minimized Boolean expression in sum
of-products form for the seven-segment decoder. See section A.1 on page 2.
• Use K-map to minimize the equation for each output.
• Submit your pre-lab 2 work (take a picture of your work on paper (please make sure
that it is readable), word doc file (if you type it), pdf) on the designated D2L
Assignment Dropbox.

Lab 2 Due Date: 11.59 PM on September 18, 2022 in the designated D2L Assignment Dropbox

Code and video submission: Submit the following files to the designated Dropbox 1) Verilog
(.v) file – using Procedural assignment statement of your seven-segment decoder. 2) Verilog
(.v) file for Testbench of your seven-segment circuit (Part a) in lab overview) 3) .xdc file for
your seven-segment circuit (Part a) in Lab overview)
4) Video of your seven-segment circuit when it is working (show several working examples)
5) Video of your two-digit display circuit (Part b in Lab Overview)

Files available on D2L under Lab 2 module

• Template Verilog Module for a seven-segment decoder (SevenSegment.v)
• Verilog Module for 2-digit display (TwoDigitDisplay.v)
• Constraint file (TwoDigitDisplay.xdc)

Reference: On D2L, under “Xilinx_Vivado_BASYS3Baord”, basys3_rm.pdf (section 8: Basic I/O

page 14-17)

Lab Overview
In this lab assignment,
a) You will first design, functionally simulate, and implement a seven-segment decoder on the
BASYS3 board. The seven-segment decoder has 4 inputs and 7 outputs. It receives a 4-bit
input number and activates the appropriate segments of the display such that the decimal
value of the input is shown.
b) Your designed seven-segment decoder module will then be used in the circuit that can
display 2-digit numbers (TwoDigitDisplay.v). This circuit will also be implemented on the
BASYS3 board.

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Part a) seven-segment decoder

a.1) Follow the combinational logic design process to design the seven-segment
decoder
• Create the truth table
• Create the Boolean expression in sum of products format (optimize/minimize
it using K map or Boolean Algebra properties)

Figure 1: seven-segment display

resource: https://reference.digilentinc.com/_media/reference/programmable-logic/basys-3/basys3_rm.pdf

The BASYS3 board contains one four-digit common anode seven-segment LED display. Each
display digit has 7 segments called A, B, C, …, G. Each segment can be activated independently
such that they can be used to display number 0 – 9 as shown in Figure 1.

To activate each segment (make it light up), logic 0 is used.

For example,
• if the 4-bit input (n3, n2, n1, n0 in the truth table below) is 0001, we want to activate
segment B and C to make the display show 1. Therefore, the outputs are A = 1, B =
0, C = 0, D = 1, E = 1, F = 1, G = 1.
• if the 4-bit input (n3, n2, n1, n0 in the truth table below) is 0110 = 6, we want to
activate every segment EXCEPT segment B to make the display show 6. Therefore,
the outputs are A = 0, B = 1, C = 0, D = 0, E = 0, F = 0, G = 0.

Next page is the truth table (for you to complete). After you complete the truth table,
write a logic equation for EACH output (use K-map (or Boolean Algebra properties) to
find the optimized/minimized Boolean expression for each output (segment).
When using K-map to find the minimized logic equation, you still group/circle cells with
logic 1 in order to write the equation in the sum-of-products format.

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Note:
1) When the decimal values of the 4-bit number are 10 -15, all segments/outputs are set to 1
(to make them NOT light up). Recall that logic 0 is used to make an LED lit up.
2) In the table below, the inputs are called numin[3], numin[2], numin[1], numin[0] such that
they are matched with the name that you will use in the given Verilog template. However,
for your work by hand (writing a simplified logic equation for each output), you can use n3,
n2, n1, and n0 instead. The outputs are called segout[6], segout [5], …, segout [0] instead
of A, B, …, G, respectively.

numin[3] numin[2] numin[1] numin[0] segout[6] segout[5] segout[4] segout[3] segout[2] segout[1] segout[0]

A B C D E F G
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0 1 1 1 1 1 1 1
1 0 1 1 1 1 1 1 1 1 1
1 1 0 0 1 1 1 1 1 1 1
1 1 0 1 1 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1

a.2) Write the Verilog code using a given template on D2L (under lab 2) called SevenSegment.v
Note: you MUST use the given template and make sure that the module is named “SevenSegment”.
Otherwise, your circuit will NOT work when you move to Part b of this lab.
In the SevenSegment.v file, you will see the following:
module SevenSegment(numin, segout);
input [3:0] numin;
output reg [6:0] segout; //segout[6] is segment A, segout[5] is B, segout[4] is C,
//segout[3] is D, segout[2] is E, segout[1] is F, segout[0] is G
always @(numin)
begin
//code for segment A is written (for you as an example) below
segout[6] <= (numin[3]& numin[1]) | (numin[3]& numin[2]) |
(numin[2]& ~numin[1]& ~numin[0]) |
(~numin[3]& ~numin[2]& ~numin[1]& numin[0]);

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//Write the code for segment B to C below

//code for segment B
// …
//code for segment G
dnd
endmodule

A multi-bit (vector) signal in Verilog:

Consider [3:0] numin in the code template above,
the signal numin has 4 bits, for example, if numin = 0110, it means that
numin[3] numin[2] numin[1] numin[0]
0 1 1 0
The output is defined as [6:0] segout where segout[6] corresponds to segment A of the seven
segment display.
Additionally, the Verilog code for segment A (segout[6]) is already given to show how you can
use each individual bit of the multi-bit signal to write your logic equation.

How do I get that equation? For segment A (segout[6]),

Note: Even though we turn on the LED using logic 0, when writing the equation (or use K-map),
we still group 1’s to obtain the minimized SOP format.

a.3) Write a testbench to functionally simulate your Verilog code of your designed seven
segment decoder. There should be 16 input combinations in the testbench since there are 4
inputs in the 7-segment decoder to exhaustively test all possible combinations of 4-bit inputs.
When you write your testbench, use the following template code to get started.
module SevenSegment_tb();
reg [3:0] numin_tb; //vector signal is also used in the testbench
wire [6:0] segout_tb;
SevenSegment m1(numin_tb, segout_tb); //calling a module to test on
initial
begin
//case 0

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numin_tb = 4'b0000; //4'b – b is for binary and 4 is for 4-bit #10
//case 1
numin_tb = 4'b0001;
// use this idea for other combinations (all combinations of inputs)
end
endmodule

a.4) If the waveform is correct, create and write .xdc file to assign pin numbers to the
inputs and outputs of your designed circuit.
- For the 4 inputs, pick 4 switches (prefer SW3, SW2, SW1 and SW0)
- For the 7 outputs or segments, as shown in the picture of pin assignments below, use
pin W7 for segment A (segout[6] in your Verilog code) (CA in the picture below),
pin W6 for segment B (segout[5]) (CB in the picture below), … to
pin U7 for segment G (segout[0]) (CG in the picture below)

Figure 2: Pin assignments on Basys3 board

resource: https://reference.digilentinc.com/_media/reference/programmable-logic/basys-3/basys3_rm.pdf
One example of assigning pin W7 to segment A (segout[6])
set_property IOSTANDARD LVCMOS33 [get_ports {segout[6]}]
set_property PACKAGE_PIN W7 [get_ports {segout[6]}]

a.5) Implement it on BASYS3 board. If it works, all four seven-segment digits should
display the decimal number corresponding to the binary number that you enter using the 4
switches. For example,
- if you have all 4 switches are in the down position (representing binary of 0000 or decimal of

0), you should see in all 4 digits on the BASYS3 board.

- if you have all 4 switches, SW3, SW2, SW1 and SW0, are in the down, down, up, up position,
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respectively (representing binary of 0011 or decimal of 3), you should see in all 4 digits
on the BASYS3 board.
Once work, take a video of how your board works when you enter a few numbers by moving
the 4 switches up or down representing each decimal or binary value.

Part b) Implement 2-digit display on the BASYS3 board

To implement the display for two digits (00 – 99). Your designed seven-segment decoder in
part a) will be used as a module in this circuit.

b.1) Get the two following files from lab 2 folder on D2L:
1) TwoDigitDisplay.v and
2) TwoDigitDisplay.xdc

In TwoDigitDisplay.v, the inputs that you will use is [6:0] Number since the decimal 00-99
can be represented by 7-bit binary number. The part of the code is given below.

module TwoDigitDisplay(Clk, Number, out7, en_out);

input Clk;
input [6:0] Number;
output [6:0] out7; //seg a, b, ... g
output reg [3:0] en_out;

• You can use the same Vivado Project, use “Add Sources” to add or create design sources and
then click Add files. Then add TwoDigitDisplay.v from the folder that you save it into the
project (make sure that your “SevenSegment.v” code is still in the project).

• Right-click on the “TwoDigitDisplay.v” file under Design Sources (Project Manager) and
choose “set as Top”. This is to make TwoDigitDisplay module the top-level design of the
Vivado project. If working, you should see the following two files in Design Sources. Observe
the three dots (signify “top level”) in front of the TwoDigitDisplay.v file

• Use “Add Sources” to Add or Create constraints then click Add files. Then add
TwoDigitDisplay.xdc into the project. If working, you should see the followings in Design
Sources.

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In TwoDigitDisplay.xdc, the pins are already mapped for you – you can start using this file in
your Vivado project. Below is an explanation on how each inputs and outputs of the
TwoDigitDisplay are mapped to the pins on the Basys3 board.
▪ Clk is mapped to pin W5 (100 MHz oscillator)
▪ SW6 – SW0 (the last 7 switches on the BASYS3) are mapped to inputs Number[6] –
Number[0], respectively.
o Number[6], Most Significant Bit (MSB) of a given number, is mapped to SW6 on
the board which is pin number W14
o Number[0], Least Significant Bit (LSB) of a given number, is mapped to SW0 on
the board which is pin number V17
▪ The pin assignments for the two multi-bit outputs are as follows:
o For the output [3:0] en_out,
▪ bit en_out[3] connects to pin W4 in Figure 2 (page 4)
▪ bit en_out[2] connects to pin V4 in Figure 2 (page 4)
▪ bit en_out[1] connects to pin U4 in Figure 2 (page 4)
▪ bit en_out[0] connects to pin U2 in Figure 2 (page 4)
o For the output [6:0] out7,
▪ bit out7[6] connects to pin W7 in Figure 2 (page 4)
▪ bit out7[5] connects to pin W6 in Figure 2 (page 4)
▪ bit out7[4] connects to pin U8 in Figure 2 (page 4)
▪ bit out7[3] connects to pin V8 in Figure 2 (page 4)
▪ bit out7[2] connects to pin U5 in Figure 2 (page 4)
▪ bit out7[1] connects to pin V5 in Figure 2 (page 4)
▪ bit out7[0] connects to pin U7 in Figure 2 (page 4)
The picture below shows the display and the switches on the BASYS3 board that you use.

resource: https://reference.digilentinc.com/_media/reference/programmable-logic/basys-3/basys3_rm.pdf
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b.2) Click on Run Synthesis, Run Implement and Generate Bitstream to implement this 2-digit
display circuit to the BASYS3 board. Check to see that the 2 digits displayed correctly correspond to
the 7-bit binary number (from using 7 switches above).
Enter several binary numbers using switches and make sure that the correct decimal values
(corresponding to its binary number) are displayed on the display. If working, take a video (of a few
input examples) and submit it on the designated D2L Dropbox.

Grading Rubrics
a.1) (Pre-lab) Create the truth table and derive the maximum of 20 out of 100 points
optimized/minimized Boolean expression in sum of
products form for the seven-segment decoder

a.2) Write Verilog code for your designed 7-segment decoder maximum of 40 out of 100 points

a.3) You can write a testbench to perform maximum of 60 out of 100 points
- behavioral simulation of your Verilog code for the
7- segment decoder.
- after the above is working correctly, also run
synthesis and perform the post-synthesis functional
simulation

a.4) You can write a .xdc file to assign the pin numbers maximum of 70 out of 100 points
to the inputs and outputs of the 7-seven segment
decoder and download to the board. The 7-seven
segment

a.5) You can generate bitstream and the seven- maximum of 80 out of 100 points
segment decoder is correctly working on the BASYS3
board.

b) You can follow the steps in part b) to download the maximum of 100 out of 100
2- digit display on the BASYS3 board. The 2-digit points
display is correctly working.