Lab Task

Task-1

• Design full adder using dataflow modelling and Implement it

using DE2-115 FPGA Board.
• Verify the logic using Switches & LED.
Task-1 : Solution

module fullad_dat(a,b,c,s,cy);
input a,b,c;
output s,cy;
assign s = a ^ b ^ c;
assign cy = (a & b)| (b & c) | (c & a);
endmodule
Task-2

Design a Four bit adder using Structural Level Verilog and

implement the same using DE2-115 board
 Task-2 - Solution
module fulladd(a,b,c,s,cy);
input a,b,c;
output s,cy;
assign s = a ^ b ^ c;
assign cy = (a & b)| (b & c) | (c & a);
endmodule

module add (a,b,cin,sum,carry);

input [3:0] a,b;
output [3:0] sum;
input cin;
output carry;
wire c1,c2,c3;
fulladd f1(.a(a[0]),.b(b[0]),.c(cin),.s(sum[0]),.cy(c1));
fulladd f2(.a(a[1]),.b(b[1]),.c(c1),.s(sum[1]),.cy(c2));
fulladd f3(.a(a[2]),.b(b[2]),.c(c2),.s(sum[2]),.cy(c3));
fulladd f4(.a(a[3]),.b(b[3]),.c(c3),.s(sum[3]),.cy(carry));
endmodule
Dr.K.Sivasankaran 5
Task-3

Design 4:1 Multiplexer using 2:1 Multiplexer and Implement the

design using DE2-115 board.
 Task-3 - Solution
module twmux (a,b,s,y);
input a,b,s;
output y;
wire y,s1,w1,w2;
not n1(s1,s);
and a1(w1,a,s);
and a2 (w2,b,s1);
or o1(y,w1,w2);
endmodule

module frmux (a,b,c,d,se1,se2,y);

input a,b,c,d,se1,se2;
output y;
wire y,se1,se2,w1,w2;
twmux t1(.a(a), .b(b), .s(se1), .y(w1) );
twmux t2(.a (c), .b(d), .s(se1), .y(w2) );
twmux t3(.a(w1), .b(w2), .s(se2), .y(y));
endmodule
 Task-4
• The objective is to display a character on a 7-segment display. The specific
character displayed depends on a two-bit input. Figure shows a 7-
segment decoder module that has the two-bit input c1 c0. This decoder
produces seven outputs that are used to display a character on a 7-
segment display.
• Table lists the characters that should be displayed for each valuation of
c1c0 for your DE-2 115 board.
• Three characters are included plus the ‘blank’ character, which is selected
for code 11.
Task-4
The seven segments in the display are identified by the indices 0 to 6 shown
in the figure. Each segment is illuminated by driving it to the logic value 0. You
are to write a Verilog module that implements logic functions that represent
circuits needed to activate each of the seven segments. Use only simple
Verilog assign statements in your code to specify each logic function using a
Boolean expression.
Task-4 - Solution

module char_7seg (SW, HEX0);

input [1:0] SW;
output [0:6] HEX0;
assign HEX[0] = ~(~SW[1] & SW[0]);
assign HEX[1] = SW[0];
assign HEX[2] = SW[0];
assign HEX[3] = SW[1];
assign HEX[4] = SW[1];
assign HEX[5] = ~(~SW[1] & SW[0]);
assign HEX[6] = SW[1];
endmodule
Task-5

Consider the circuit shown in Figure. It uses a two-bit wide 3-to-1 multiplexer
to enable the selection of three characters that are displayed on a 7-segment
display. Using the 7-segment decoder from Task -4 this circuit can display the
characters d, E, ‘blank’ and 0, 1, or 2 depending on your DE2115 board. The
character codes are set according to Table by using the switches SW5 -SW0,
and a specific character is selected for display by setting the switches SW9-
SW8.
 Task-5 - Solution

module part5 (SW, HEX0);

input [9:0] SW; // toggle switches
output [0:6] HEX0; // 7-seg displays
wire [1:0] M;
// module mux_2bit_3to1 (S, U, V, W, M);
mux_2bit_3to1 M0 (SW[9:8], SW[5:4], SW[3:2], SW[1:0], M);
// module char_7seg (C, Display);
char_7seg H0 (M, HEX0);
endmodule
 Task-5 - Solution

module mux_2bit_3to1 (S, U, V, W, M);

input [1:0] S, U, V, W;
output [1:0] M;
wire m_0, m_1;
// 3-to-1 multiplexer for bit 0
assign m_0 = (~S[0] & U[0]) | (S[0] & V[0]);
assign M[0] = (~S[1] & m_0) | (S[1] & W[0]);
// 3-to-1 multiplexer output

// 3-to-1 multiplexer for bit 1

assign m_1 = (~S[0] & U[1]) | (S[0] & V[1]);
assign M[1] = (~S[1] & m_1) | (S[1] & W[1]);
// 3-to-1 multiplexer output
endmodule
 Task-5 - Solution

module char_7seg (C, Display);

input [1:0] C;
output [0:6] Display;
assign Display[0] = ~(~C[1] & C[0]);
assign Display[1] = C[0];
assign Display[2] = C[0];
assign Display[3] = C[1];
assign Display[4] = C[1];
assign Display[5] = ~(~C[1] & C[0]);
assign Display[6] = C[1];
endmodule