Laboratory Exercise Dig5

Numbers and Displays

This is a two week lab exercise in designing combinational circuits that can perform binary-to-decimal
number conversion and binary-coded-decimal (BCD) addition. Read these notes carefully before starting since
this latest revision contains lots of hints ☺

Part I

We wish to display on the 7-segment displays HEX3 to HEX0 the values set by the switches SW[15:0]. Let
the values denoted by SW[15:12], SW[11:8], SW[7:4] and SW[3:0] be displayed on HEX3, HEX2,
HEX1 and HEX0, respectively. Your circuit should be able to display the digits from 0 to 9, and should treat the
values 1010 to 1111 as don’t-cares.
1. Create a new project, Dig5, which will be used to implement the desired circuit on the Altera DE2 board.
The top level module is where the definition of your design begins. This project should use a top level
module called Dig5 which is defined in the file Dig5.v. Note that it is customary (but not essential) to
use the same name for the Quartus project and the top level module. The top level module has standard
port names such as SW, LEDR, LEDG, HEX0 etc. since it represents the FPGA Cyclone II device that
connects to the switches, LEDs and displays on the DE2 board via fixed circuit board tracks. Define a
new module BCD with a 4 bit input port in and 7 bit output port Hex. The BCD module can be placed
within the file Dig5.v but below the Dig5 module definition and can use an always block containing a
case statement (the case statement can represent a truth table for the logic function similar to that used in
Lab Dig4). Instantiate (ie make a copy of) the BCD module in the top level module Dig5 for each HEX
display digit. The intent of this exercise is to use a high level Verilog behavioural description of the logic
function and let the Quartus compiler do the optimisation of the design rather than you optimising
complex Boolean logic expressions.
2. Write the Verilog file Dig5.v that provides the necessary functionality. Include this file in your project and
assign the pins on the FPGA to connect to the switches and 7-segment displays. The procedure for making
pin assignments is described in the Lab Dig3 or Quartus II Introduction using Verilog Design, which is on
the University Program section of Altera’s web site.

3. Compile the project and download the compiled circuit into the FPGA chip. Test the functionality of your
design by toggling the switches and observing the displays. Off campus students use the testbench on
Moodle called Dig5part1_tb.v and include your BCD module at the top of the file. Run the simulation to
completion and plot waveforms of the error_count (should be 0) disp_student and disp (these should be
equal) as binary representations (the default). Note that the implementation of the altBCD module should
be different to your implementation. Show the testbench and waveforms of ModelSim and $display
messages to your demonstrator for marking.

Checked by demonstrator, initial here:

Part II

You are to design a circuit that converts a four-bit binary number V[3:0] into its two-digit decimal equivalent d1 d0. Table 1
shows the required output values. A partial design of this circuit is given in Figure 1a.

Circuit B displays the most significant digit (either 1 or 0) on one seven segment display, depending on the input V. To create
the desired output for the least significant digit, if V is less than or equal to 9, the input to the BCD module (from part 1) is
described by the input binary value (V). If V is greater than 9, circuit A converts V into the desired binary value, as described by
Table 1, which is then inputted to the BCD module.

You are to complete the design of this circuit by first creating a Verilog module called part2 which includes the comparator,
multiplexers, and circuit A (do not include circuit B or the BCD module at this point). Your Verilog module part2 should have
the four-bit input V, the four-bit output M and the output z as ports. Your Verilog code should use high level Verilog.

Binary value Decimal digits

0000 0 0
0001 0 1
0010 0 2
... ... ...
1001 0 9
1010 1 0
1011 1 1
1100 1 2
1101 1 3
1110 1 4
1111 1 5

Table 1. Binary-to-decimal conversion values.

part2

BCD

Figure 1a. Partial design of the binary-to-decimal conversion circuit.

 Perform the following steps:

1. Use the same project as part 1 and write the new Verilog module called part21. The part2 module will start out
with the port names V, m, and z – use these port names that match the problem description. Instantiate the
module part2 in your existing top level module, Dig5. Hints: You can use comparisons in a Verilog
assign statement. For example
assign x = (y > 3’d5); // x is 1 when the 3 bit y is greater than 5 – the compiler generates logic for you!
Circuit A can be implemented with an always block containing a case statement representing the logic
function truth table. The multiplexer can be implemented with an always block containing an if-else
statement. See Figure 1b for a Verilog template to get started. This file is on Moodle as LabDig5Fig1b.v.

module part2(V, m, z);

input [3:0] V;
output reg [3:0] m;
output z;

// comparator
assign z = ………………. ;

// Circuit A
reg [2:0] Aout; // internal signal from output of
// Circuit A – must be reg since
// driven from always block.
always @(V)
case(V[2:0])
3'b010: Aout= ……….;
……… // other cases here
default: Aout= ……….;
endcase

//multiplexer
always@(V, Aout, z)
if (……) m = {1'b0, Aout}; // concatenates 1 bit 0
// with 3 bit Aout to
// make 4 bit vector
else m = …….;
endmodule

Figure 1b. Verilog Template for first half of Part2.

2. Compile the circuit and use functional simulation to verify the correct operation of your part2 module that
includes only the comparator, multiplexers, and circuitA. You may use the following testbench to create
waveforms to test all input combinations. To use this, create a new file (File > New > Verilog HDL file).
Copy this code and save as part2_testbench.v. In the Project Navigator subwindow, under files, right
click on this file and select “Set as Top-Level Entity”. In the Tasks pane, change flow to RTL
Simulation. Double click on RTL Simulation, this should start Modelsim. In Modelsim, under library,
click work, then double click part2_testbench. Start the waveform viewer (View > wave), then drag and
drop inputV, outputM and outputZ to the waveform viewer. (For greater explanation, look again at lab
Dig3. Off campus students can create a project within ModelSim to run the testbench as per lab Dig3).

Show your demonstrator the waveform so they can ensure this is working correctly.

1
You can remove previous instantiations from part 1 by placing a comment // at the start of each line.
 `timescale 1ns / 1ps

module part2_testbench;

reg[3:0] inputV;
wire[3:0] outputM;
wire outputZ;

part2 test_part2(.V(inputV),.m(outputM),.z(outputZ));

initial begin
inputV = 0;
end

always begin
#10
inputV = inputV+1;
end

integer count;
initial begin
count = 0;
end

always begin
#10
if (count === 16) begin
#10 $display("Done with test.");
//$finish;
end
count=count+1;
end

endmodule

Checked by demonstrator, initial here:

 On campus students follow steps 3-6 below.
3. Set Dig5 as your top level module again: From the Project Navigator, select Files tab and right click on
the Dig5.v and set as top level module. Compile and test the design using the SW inputs and LEDG
output on the DE2 board.
4. Augment your Verilog code to include circuit B in Figure 1 as well as the BCD module. I ns t a n t i a t e t h e
mo d u l e i n yo u r D i g 5 t o p l e v e l mo d u l e t o co n n e c t the input V to SW[3:0] and the outputs to
the displays HEX1 and HEX0 to show the values of decimal digits d 1 and d0. Make sure to include in your
project the required pin assignments for the DE2 board.

5. Recompile the project, and then download the circuit into the FPGA chip.
6. Test your circuit by trying all possible values of V and observing the output displays.

Off campus students follow these instructions: Use the supplied testbench on Moodle with filename
Dig5part2_tb.v (not the part2_testbench.v in these lab notes) and include your augmented module that
includes circuit B in the file. You will need to rename your module as part2withCctBandBCD and this
should include instantiations of part2 (with circuit A) and circuit B and the BCD. Run the simulation to
completion and plot waveforms of the error_count (should be 0) V and hex0, hex1, hex0a and hex1a (hex0
and hex0a plus hex1 and hex1a should be both equal) as binary representations (the default). Note that the
implementation of the part2alt module should be different to your implementation. Save the testbench and
show your demonstrator ModelSim showing the waveforms and $display messages produced by ModelSim.

Checked by demonstrator, initial here:

Part III

Figure 2a shows a circuit for a full adder, which has the inputs a, b, and c i, and produces the outputs s and c o .
Parts b and c of the figure show a circuit symbol and truth table for the full adder, which produces the two-bit
binary sum co s = a + b + ci. Figure 2d shows how four instances of this full adder module can be used to design a
circuit that adds two four-bit numbers. This type of circuit is usually called a ripple-carry adder, because of
the way that the carry signals are passed from one full adder to the next. Write Verilog code that implements this
circuit, as described below:

1. Write a Verilog module for a 4 bit ripple adder and instantiate at the top-level Verilog connected as follows.
Use switches SW[7:4] and SW[3:0] to connect to the inputs A and B, respectively. Use SW[8] for the
carry-in cin of the adder. Connect the SW switches to their corresponding red lights LEDR, and connect
the outputs of the adder, cout and S, to the green lights LEDG.

2. Include the necessary pin assignments for the DE2 board, compile the circuit, and download it into the
FPGA chip. Test your circuit by trying different values for numbers A, B, and c in. Off campus students:
instead use the supplied testbench on Moodle called Dig5part3_tb.v and include your module in the
file. You may need to rename your module as FourBitRippleAdder and this should include
instantiations of your full adder. Run the simulation to completion and plot waveforms of the
error_count (should be 0) a, b, cin, s_alt, s_student, cout_alt and cout_student as binary
representations (the default). Note that the implementation of the AltFourBitRippleAdder module
should be different to your implementation. Save the testbench and show your demonstrator a
screenshot of ModelSim showing the waveforms and $display messages.

Checked by demonstrator, initial here:

Figure 2. A ripple-carry adder circuit.

Part IV

In part II we discussed the conversion of binary numbers into decimal digits. It is sometimes useful to build
circuits that use this method of representing decimal numbers, in which each decimal digit is represented using
four bits. This scheme is known as the binary coded decimal (BCD) representation. As an example, the decimal
value 59 is encoded in BCD form as 0101 1001.
You are to design a circuit that adds two BCD digits. The inputs to the circuit are BCD numbers A and B,
plus a carry-in, cin. The output should be a two-digit BCD sum S1 S0 . Note that the largest sum that needs to be
handled by this circuit is S1S0 = 9 + 9 + 1 = 19. Perform the steps given below.
1. Modify your Quartus II project to include your BCD adder module. You should use the four-bit adder
circuit from part III to produce a four-bit sum and carry-out for the operation A + B. A circuit that
converts this five-bit result, which has the maximum value 19, into two BCD digits S 1S0 can be designed
in a very similar way as the binary-to-decimal converter from part II.
2. Use switches SW[7:4] and SW[3:0] for the inputs A and B, respectively, and use SW[8] for the
carry-in. Connect the SW switches to their corresponding red lights LEDR, and connect the four-bit sum
and carry-out produced by the operation A + B to the green lights LEDG. Display the BCD values of A and
B on the 7-segment displays HEX6 and HEX4, and display the result S 1S0 on HEX1 and HEX0.
3. Since your circuit handles only BCD digits, check for the cases when the input A or B is greater than nine.
If this occurs, indicate an error by turning on the green light LEDG[8]. Hint: you can use a single
assign statement as you did in Part 2;
4. Check you have loaded the necessary pin assignments for the DE2 board, compile the circuit, and download it into the
FPGA chip. Test your circuit by trying different values for numbers A, B, and c in. Off campus students: use the
supplied testbench on Moodle and include your module in the file. You may need to rename your module BCDadder
and this should include an instantiation of your FourBitRippleAdder. Run the simulation to completion and plot
waveforms of the error_count (should be 0) a, b, cin, S1_student, S0_student, S1alt, S0alt and error_student,
error_alt as binary representations (the default). Note that the implementation of the AltBCDadder module should
be different to your implementation. Save the testbench and show your demonstrator ModelSim showing the
waveforms and $display messages.

Checked by demonstrator, initial here:

Part V

Design a circuit that can add two 2-digit BCD numbers, A 1A0 and B1B0 to produce the three-digit BCD sum
S2S1S0. Use two instances of your circuit from part IV to build this two-digit BCD adder. Perform the steps
below:
1. Use switches SW[15:8] and SW[7:0] to represent 2-digit BCD numbers A1A0 and B1B0, respectively.
The value of A1A0 should be displayed on the 7-segment displays HEX7 and HEX6, while B 1B0 should
be on HEX5 and HEX4. Display the BCD sum, S2S1S0, on the 7-segment displays HEX2, HEX1 and
HEX0.
2. Make the necessary pin assignments and compile the circuit.
3. Download the circuit into the FPGA chip, and test its operation. Off campus students: Use the supplied
testbench on Moodle called Dig5part5_tb.v and include your module in the file. You may need to rename
your module to BCDadder2digit and this should include an instantiations of BCDadder from the previous
part. Run the ModelSim simulation to completion and plot waveforms of the error_count (should be 0) A1,
A0, B1, B0, S1_student, S0_student, S1alt, S0alt, error_student and error_alt as binary representations (the
default). Note that the implementation of the altBCDadder2digit module should be different to your
implementation. Show your demonstrator ModelSim showing the waveforms and $display messages.

Checked by demonstrator, initial here:

Part VI

In part V you created Verilog code for a two-digit BCD adder by using two instances of the Verilog code for a
one-digit BCD adder from part IV. A different approach for describing the two-digit BCD adder in Verilog code
is to specify an algorithm like the one represented by the following pseudo-code:

1 T0 = A0 + B0
2 if (T0 > 9) then
3 Z0 = 10;
4 c1 = 1;
5 else
6 Z0 = 0;
7 c1 = 0;
8 end if
9 S0 = T0 − Z0

10 T1 = A1 + B1 + c1
11 if (T1 > 9) then
12 Z1 = 10;
13 c2 = 1;
14 else
15 Z1 = 0;
16 c2 = 0;
17 end if
18 S1 = T1 − Z1
19 S 2 = c2

It is reasonably straightforward to see what circuit could be used to implement this pseudo-code. Lines 1, 9, 10,
and 18 represent adders, lines 2-8 and 11-17 correspond to multiplexers, and testing for the conditions T 0 > 9
and T1 > 9 requires comparators. You are to write a Verilog always block that corresponds to this pseudo-code.
Note that you can perform addition operations in your Verilog code instead of the subtractions shown in lines 9
and 18. For example with 4 bit arithmetic, subtracting 10 is the same as adding 6. Eg 13-10 = 3 and 13+6 = 3
(mod 16) - ie the result is truncated to 4 bits. The intent of this part of the exercise is to examine the effects of
relying on the Verilog compiler to design the circuit by using if-else statements along with the Verilog > and +
operators. Do not use subtraction even though it is supported in Verilog. Perform the following steps:
1. Create a new module part6 for your Verilog code. Instantiate part6 using the same switches, lights, and
displays as in part V. Compile your circuit.
2. Use the Quartus II menu T o o l s - > N e t l i s t V i e we r s - > RTL Viewer to examine the circuit produced
by compiling your Verilog code. Compare the circuit to the one you designed in Part V.

3. Download your circuit onto the DE2 board and test it by trying different values for numbers A 1A0 and
B1 B0 . Off campus students: Use the supplied testbench on Moodle called Dig4part6.v and
include your module in the file. You may need to rename your module as BCDadder2digit. Run
the ModelSim simulation to completion and plot waveforms of the error_count (should be 0) A1,
A0, B1, B0, S1_student, S0_student, S1alt, S0alt, error_student and error_alt as binary
representations (the default). Note that the implementation of the altBCDadder2digit module
should be different to your implementation. Show your demonstrator ModelSim showing the
waveforms and $display messages.

Checked by demonstrator, initial here:

Part VII

Design a combinational circuit that converts a 6-bit binary number into a 2-digit decimal number represented in
the BCD form. Use switches SW[5:0] to input the binary number and 7-segment displays HEX1 and HEX0
to display the decimal number. Implement your circuit on the DE2 board and demonstrate its functionality.

Hint: Use a single always block to define the two BCD output digits. Within that always block you can use a
series of if statements testing value of the input corresponding to each change in the 10’s BCD digit. Note that
the values at the end of the always block after each statement “executes” determine the logic function. This
means an output value of the always block can be changed multiple times within the block, but it is only the last
change that matters. So multiple if statements can trigger in the always block with each one overwriting previous
one.

Off campus students: Use the supplied testbench on Moodle and include your module in the file. You may
need to rename your module to Convert6bitTo2BCD. Run the ModelSim simulation to completion and plot
waveforms of the error_count (should be 0) in, D1student, D0student, D1alt and D0alt as binary
representations (the default). Note that the implementation of the AltConvert6bitTo2BCDmodule should be
different to your implementation – the Alt version is quite inefficient since the division / and modulus %
operators require many logic blocks to implement in practice and should be avoided for synthesis. The Alt
version is merely for checking the correct answer and is not meant to be efficient. Show your demonstrator
ModelSim showing the waveforms and $display messages.

Checked by demonstrator, initial here:

Copyright Q
c Altera Corporation. Updated for ECE2072 Monash University.