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Model FAT Question Paper

Programme : B.Tech.(ECE/ECM) Max. Marks : 100
Course code & Title : ECE2003 - Digital Logic Design Time : 3 Hours

Answer any ALL questions

Sub.
Q.No. Question Description Marks
Sec.

1. (a) Perform the following conversion: [4]

(i). (16.5)16 = (?)10
(ii). (673.23)10 = (?)2.

(b) If VCC = 5V, ICC(0) = 22 mA, ICC(1) = 8 mA, VIH(min) = 2V, VOH(min) = 2.4V, VOL(max) = 0.45V, [6]
VIL(max) = 0.8V, tPHL = 15 ns, tPLH = 22 ns, IIH = 40 µA, IOH = 5.2 mA, Calculate
(i). Noise Margin logic ‘1’ and logic ‘0’
(ii). Power Dissipation and Fanout
(iii). Propogation delay

2 (a) Subtract (-22)10 from (39)10 using 2’s complement. [2]

(b) A bulb has two switches, one on the first floor and another on the second floor. It can be switched [3]
ON and OFF by any one of the two switches.What logic gate does the logic of switching the bulb
represents? Justify with truth table.

3. Given the Boolean function: [10]

F= xy′z + x′y′z + w′xy + wx′y + wxy
(i). Obtain the truth table of the given function F.
(ii). Simplify the function F to a minimum number of literals using Boolean algebra.
(iii). Draw the logic diagram from the simplified expression using NAND gate only.

4. Design a combinational logic circuit with a single output that will serve as an auto buzzer [10]
circuit. This circuit should output a HIGH signal to sound a buzzer for each of the following
conditions:
a) if the driver’s DOOR is open and the KEYS are in the ignition.
b) if the SEATBELT is not buckled, the SEAT is occupied and the KEYS are in the
ignition.
Perform the following steps to design the buzzer control unit,
(i) Draw the Truth Table to describe the circuit operation for different combination of inputs.
(ii) Obtain a simplified expression using K-map.
(iii) Implement the simplified expression with the help of logic gates.

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5. Design a partial simplified Arithmetic Logic Unit (ALU) using basic logic gates which is capable [10]
of performing the 1-bit arithmetic subtraction operation with the inclusion of borrow as
additional input. Implement the obtained logical expressions difference and borrow using 1:8
demultiplexer.

6. In the following truth table-1 given, V=1 if and only if the input is valid. What function does the [10]
truth table represent? Obtain minimized logic circuit for the given logic.

INPUTS OUTPUTS
D3 D2 D1 D0 X Y V
0 0 0 0 X X 0
0 0 0 1 0 0 1
0 0 1 X 0 1 1
0 1 X X 1 0 1
1 X X X 1 1 1
Table-1

7. (a) Answer the following based on the basic concepts of Verilog HDL. Justify your answer for each. [5]
(i). “_4to1Mux” – is a valid identifier or not?
(ii). “D_flipflop ≠ D_Flipflop” – why both are not equal?
(iii). “Y`d456” – Find the value of Y?
(iv). “A ! = = B?” – What is the logical output (0 or 1) assume A=4`b1xzz and B=4`b1xxz.
(v). “Y=(sel)? B: A” – for the conditional statement given find the value of Y, if sel=1.

(b) Write a Verilog HDL code for 4-bit ripple carry adder logic using full adder. [5]

8. Contruct a logic diagram for shift register with parallel load operations according to the following [10]
function table-2. Write a Verilog HDL and sample test bench code for the same.

Shift Load Register operations

0 0 No change
0 1 Load parallel data
1 x Shift Right
Table-2

9. In the packaging department of a cricket ball manufacturing company, the balls roll down a [10]
conveyor and get filled into the empty boxes for shipment. Capacity of each box is 6 balls. Each
ball is allowed to pass through IR scanner, which generates a one clock pulse for every ball that
crosses the scanner. Design an appropriate mod counter using T-FlipFlop to count the clock pulse
generated from scanner to indicate whether the box is full or not, so that next empty box can be
moved into the position.

10. Design mealy sequence detector to detect a sequence 1010 using D filpflop. [15]

Total marks [100]

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