Reg. No.

:
Name :

TERM END EXAMINATIONS (TEE) – February-March 2023

Programme : B.Tech.MIM Semester : Winter 2022-23
Course Title/
: Digital Logic Design/ ECE2002 Slot : E11+E12+E13
Course Code
Time : 1½ hours Max. Marks : 50

Answer ALL the Questions

Q. No. Question Description Marks

PART - A ( 30 Marks)
1 (a) Perform the following subtraction: 10

(57.75)10 - (69.25)10
using the 12-bit signed 1’s complement (8 to represent magnitude including sign bit
and 4 to represent decimal)
OR
(b) (i) Design a 4-bit parallel adder with carry look ahead logic. 6

(ii) Prove the following: 4

A ⊕ B = A’ ⊕ B’
2 (a) (i) Convert T flip flop to D flip flop 6

(ii) Write down the characteristic equation of SR flip flop 4

OR
(b) Design a synchronous MOD 6 counter with T flip-flop and check whether the counter 10
is self-starting or not?

3 (a) Draw the state diagram and state table of the sequence detector that can detect an 10
overlapping sequence ‘0110’. (you don’t need input bit stream)

OR
(b) Write the Verilog code to implement 3 to 8 Decoder. 10
Show verification waveform at least for two outputs

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 PART - B (20 Marks)

4 (i) A sequential circuit using D flip-flop and logic gates is shown in the Fig.1, 6
calculate the output for 4 clock cycle when you apply

Fig.1

X=1 and Y =1 and the clock is a negative edge trigger. Assume that initially the flip
flop is cleared.

(ii) Design a NAND gate using 2:1 Multiplexer 4

5 Design a synchronous circuit (using any flipflop) with the given state diagram in Fig.2. 10

Fig.2


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