LAB 02: IMPLEMENTATION OF BASIC COMBINATIONAL CIRCUITS

USING VERILOG
OBJECTIVE:

 To implement and simulate different combinational circuits using Verilog in Xilinx ISE
Design Suite

INTRODUCTION:
Combinational Circuits (CC) are circuits made up of different types of logic gates. A logic gate is
a basic building block of any electronic circuit. The output of the combinational circuit depends on
the values at the input at any given time. The circuits do not make use of any memory or storage
device.
For example; Half Adders, Half Subtractors, Multiplexers etc. which we will study in upcoming
labs.

IN-LAB TASKS
These In-lab tasks will help better understand the working of Verilog and Xilinx ISE.

 Task 1: Implement all logic gates in a single module in Xilinx and verify
Truth table values using Test bench and Waveform.
 Truth table:
 Block diagram:
 Mathematical modeling:
 Verilog code: (sub headings: Font size: Time News Roman-12)
 RTL schematic:
 Test bench:
 Waveform:
 Wave description: (based on different combination of inputs)

Varilog code:
TRUTH TABLE:
Task 2: Implement the following circuit in Xilinx and verify Truth table values using Test
bench and Waveform

Truth table:
Block diagram:
Mathematical modeling:
Verilog code: (sub headings: Font size: Time News Roman-12)
RTL schematic:
Test bench:
Waveform:
Wave description: (based on different combination of inputs)
Truth Table:

POST LAB TASKS

 Task 1: Implement the following logic circuit in Xilinx ISE Design Suite.
Also write test bench to verify your results. At the end, compare your results
with Truth table.
 Truth table:
 Block diagram:
 Mathematical modeling:
 Verilog code: (sub headings: Font size: Time News Roman-12)
 RTL schematic:
 Test bench:
 Waveform:
 Wave description: (based on different combination of inputs)
Module Code:
So here varifing that

 When all inputs OFF then its result ON

 When f ON except all inputsthen output is OFF

 When e is ON except all inputs then output is also OFF

 When e & f is ON except all inputs then output is ON

Truth Table:

A B C D E F OUTPUT
0 0 0 0 0 0 1
0 0 0 0 0 1 0
0 0 0 0 1 0 0
0 0 0 0 1 1 1