Digital System Design LAB 2

IMPLEMENTATION OF COMBINATIONAL CIRCUITS

OBJECTIVES

• To write Verilog module for digital circuits at behavioral level

• To use case statements in Verilog HDL.
• To use if else statements in Verilog HDL.
• To write Verilog module for Decoders.
• To write Verilog module for Priority Encoders.
• To write Verilog module for Multiplexers.

INTRODUCTION

A number of standard combinational logic functions have been developed for digital circuits
that represent many of the useful tasks that can be performed with digital circuits.

Decoders detect the presence of particular binary states and can activate other circuits
based on their input values or can convert an input code to a different output code.

Encoders generate a binary or binary coded decimal (BCD) code corresponding to an active
input.

Multiplexers and de-multiplexers are used for data routing. They select a transmission path
for incoming or outgoing data, based on a selection made by a set of binary-related inputs.

DECODERS

The general function of a decoder is to activate one or more circuit outputs upon detection
of a particular digital state. The simplest decoder is a single logic gate, such as a NAND or
AND, hose output activates when all its inputs are HIGH. When combined with one or more
inverters, a NAND or AND can detect any unique combination of binary input values. An
extension of this type of decoder is a device containing several such gates, each of which
responds to a different input state. Usually, for an n-bit input, there are 2n logic gates, each
of which decodes a different combination of input variables. Some types of decoders
translate binary inputs to other forms, such as the decoders that drive seven-segment
numerical displays. The decoder has one output for every segment in the display. These
segments illuminate in unique combinations for each input code

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Digital System Design LAB 2

Figure 1 2-line-to-4-line Decoder with Enable

Figure 1 shows the logic circuit of a 2-line-to-4-line decoder. The circuit detects the
presence of a particular state of the 2-bit input D1D0, as shown by the truth table in Table
1. One and only one output is HIGH for any input combination, provided the enable input G
is LOW.

G(activelow) D0 D1 Y0 Y1 Y2 Y3

0 0 0 1 0 0 0

0 0 1 0 1 0 0

0 1 0 0 0 1 0

0 1 1 0 0 0 1

1 X X 0 0 0 0

Table1 Truth Table of a 2-to-4 Decoder with Enable

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Digital System Design LAB 2
Task1
A Verilog module is shown below. Create a new project using Xilinx ISE. Add this module to
project and verify it by simulating its behavior.

1. Verilog Module for 3 to 8 decoder

Module v_decoders_1 (sel, res);

Input [2:0] sel;

Output [7:0] res;

Reg [7:0] res;

Always @ (sel or res)

Begin

Case (sel)

3’b000: res = 8'b00000001;

3’b001: res = 8'b00000010;

3’b010: res = 8'b00000100;

3’b011: res = 8'b00001000;

3’b100: res = 8'b00010000;

3’b101: res = 8'b00100000;

3’b110: res = 8'b01000000;

Default: res = 8'b10000000;

End case

End

End module

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Digital System Design LAB 2

What is the purpose of using case statement in module for 3 to 8 decoder?

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Explain and record results for above Verilog module?

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Draw results from Test bench for 3 to 8 decoder? Indicate Input & Output signals?

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Digital System Design LAB 2
Task2
A Verilog module is shown below. Create a new project using Xilinx ISE. Add this module to
project and verify it by simulating its behavior.

2. Module v_decoders_2 (sel, res);

Input [2:0] sel;

Output [7:0] res;

Reg [7:0] res;

Always @ (sel)

Begin

Case (sel)

3’b000: res = 8'b11111110;

3’b001: res = 8'b11111101;

3’b010: res = 8'b11111011;

3’b011: res = 8'b11110111;

3’b100: res = 8'b11101111;

3’b101: res = 8'b11011111;

3’b110: res = 8'b10111111;

Default: res = 8'b01111111;

Encase

End

End module

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Digital System Design LAB 2

What is the difference between module v_decoders_2 and module v_decoders_1?

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Explain and record results for above Verilog module? How this module will be
implemented at hardware level?

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Draw results from Test bench for 3 to 8 decoder? Indicate Input & Output signals?

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Digital System Design LAB 2
PRIORITY ENCODER

The function of a digital encoder is complementary to that of a digital decoder. An encoder

activates a specified output for a unique digital input code. An encoder operates in the
reverse direction, producing a particular digital code (e.g., a binary or BCD number) at its
outputs when a specific input is activated.

Priority Encoder One solution to this problem is to assign a priority level to each input and, if
two or more are active, make the output code correspond to the highest-priority input. This
is called a priority encoder. Highest priority is assigned to the input whose subscript has the
logical value.

Priority Encoder in Verilog HDL

Module v_priority_encoder_1 (sel, code);

Input [7:0] sel;

Output [2:0] code;

Reg [2:0] code;

Always @ (sel)

Begin

If (sel [0]) code = 3'b000;

Else if (sel [1]) code = 3'b001;

Else if (sel [2]) code = 3'b010;

Else if (sel [3]) code = 3'b011;

Else if (sel [4]) code = 3'b100;

Else if (sel [5]) code = 3'b101;

Else if (sel [6]) code = 3'b110;

Else if (sel [7]) code = 3'b111;

Else code = 3'bxxx;

End

End module

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Digital System Design LAB 2

In your own words describe a priority encoder?

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Why you are using if else statements in above module?

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Explain and record results for above Verilog module?

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Draw results from Test bench for priority encoder?

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Digital System Design LAB 2
MULTIPLEXER

Multiplexers are used for a variety of applications, including selection of one data stream out
of several choices, switching multiple-bit data from several channels to one multiple bit
output, sharing data on one output over time, and generating bit patterns or waveforms.

In Verilog, you must be aware that Case statements can be full or not full, and they can
also be parallel or not parallel. A Case statement is:

• FULL if all possible branches are specified.

• PARALLEL if it does not contain branches that can be executed simultaneously.

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Digital System Design LAB 2
Tasks
For each of the module given below create a project in Xilinx ISE .Add module to the
project. Now simulate this file using ISE Simulator. Next synthesize this file using XST.

Then answer Questions given at the end of module

Full and Parallel Case

Module full (sel, i1, i2, i3, i4, o1);

Input [1:0] sel;

Input [1:0] i1, i2, i3, i4;

Output [1:0] o1;

Reg [1:0] o1;

Always @ (sel or i1 or i2 or i3 or i4)

Begin

Case (sel)

2'b00: o1 = i1;

2'b01: o1 = i2;

2'b10: o1 = i3;

2'b11: o1 = i4;

End case

End

End module

Not Full but Parallel

Module not full (sel, i1, i2, i3, o1);

Input [1:0] sel;

Input [1:0] i1, i2, i3;

Output [1:0] o1;

Reg [1:0] o1;

Always @ (sel or i1 or i2 or i3)

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Digital System Design LAB 2
Begin

Case (sel)

2'b00: o1 = i1;

2'b01: o1 = i2;

2'b10: o1 = i3;

End case

End

End module

Neither Full nor Parallel

Module notfull_notparallel (sel1, sel2, i1, i2, o1);

Input [1:0] sel1, sel2;

Input [1:0] i1, i2;

Output [1:0] o1;

Reg [1:0] o1;

Always @ (sel1 or sel2)

Begin

Case (2'b00)

sel1: o1 = i1;

sel2: o1 = i2;

End case

End

End module

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Digital System Design LAB 2
4-to-1 1-Bit MUX Using IF Statement
Module v_multiplexers_1 (a, b, c, d, s, o);

Input a, b, c, d;

Input [1:0] s;

Output o;

Reg o;

Always @ (a or b or c or d or s)

Begin

If (s == 2'b00) o = a;

Else if (s == 2'b01) o = b;

Else if (s == 2'b10) o = c;

Else o = d;

End

End module

4-to-1 MUX Using Case Statement

Module v_multiplexers_2 (a, b, c, d, s, o);

Input a, b, c, d;

Input [1:0] s;

Output o;

Reg o;

Always @ (a or b or c or d or s)

Begin

Case (s)

2’b00: o = a;

2’b01: o = b;

2’b10: o = c;

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Digital System Design LAB 2
Default: o = d;

End case

End

End module

4-to-1 MUX Using Tristate Buffers

Module v_multiplexers_3 (a, b, c, d, s, o);

Input a, b, c, d;

Input [3:0] s;

Output o;

Assign o = s [3]? a: 1’BZ;

Assign o = s [2]? b :1'bz;

Assign o = s [1]? c :1'bz;

Assign o = s [0]? d :1'bz;

end module

Explain following statement?

Assign o = s [0]? d :1'bz;

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Observations/Comments/Explanation of Results