Advanced Digital Electronics Laboratory Exp.

4
Experiment 4
Data Types in VHDL language part1
Design Example Multiplexer
Learning Objectives:
1. Some fundamental predefined VHDL data types will introduced in this experiment, with
special emphasis on those that are synthesizable.
2. How to deal with errors in VHDL code using ISE 9.2i software.
3. To design, synthesize, and simulate the operation of a 4:1 multiplexer circuit with VHDL
language.
Equipment and Materials:
1- Full version of Xilinx ISE 9.2i software installed on your laboratory personal computer.
Introduction:
VHDL is a strongly typed language, the aim of strong typing is to allow detection of errors
at an early stage of the design process. The three defined data types in VHDL are:
o Scalar types: are atomic units of information.
o Composite types: are arrays and/or records; each object of this data type can hold more
than one value
o Access types: are akin to pointers in other programming languages
o File Type: allows the user to deal with files.
All declarations of VHDL ports, signals, and variables must specify their corresponding type
or subtype shown below:

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The fundamental synthesizable VHDL data types are summarized in table:

Procedures:
1. Start Xilinx ISE 9.2 ,create a new project then create new source for VHDL Module. Prepare
an empty Entity then write the following TYPE definitions and SIGNAL declarations in the
architecture declarative part:
TYPE array1 IS ARRAY (7 DOWNTO 0) OF STD_LOGIC;
TYPE array2 IS ARRAY (3 DOWNTO 0, 7 DOWNTO 0) OF STD_LOGIC;
TYPE array3 IS ARRAY (3 DOWNTO 0) OF array1;
SIGNAL a : BIT;
SIGNAL b : STD_LOGIC;
SIGNAL x : array1;
SIGNAL y : array2;
SIGNAL w : array3;
SIGNAL z : STD_LOGIC_VECTOR (7 DOWNTO 0);
2. Determine which among the assignments in table below are legal and which are illegal
practically, by writing them in architecture code part . Briefly justify your answers. Also,
determine the dimensionality of each assignment (on both sides). Record your results by
filling the following table:
Dimension Legal or illegal
Assignment
(on each side) (why)
a <= x(2);
b <= x(2);
b <= y(3,5);
b <= w(5)(3);
y(1)(0) <= z(7);
x(0) <= y(0,0);
x <= "1110000";
a <= "0000000";
y(1) <= x;
w(0) <= y;
w(1) <= (7=>'1', OTHERS=>'0');
y(1) <= (0=>'0', OTHERS=>'1');
w(2)(7 DOWNTO 0) <= x;
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w(0)(7 DOWNTO 6) <= z(5 DOWNTO 4);
x(3) <= x(5 DOWNTO 5);
b <= x(5 DOWNTO 5);
y <= ((OTHERS=>'0'),(OTHERS=>'0'),
(OTHERS=>'0'), "10000001");
z(6) <= x(5);
z(6 DOWNTO 4) <= x(5 DOWNTO 3);
z(6 DOWNTO 4) <= y(5 DOWNTO 3);
y(6 DOWNTO 4) <= z(3 TO 5);
y(0, 7 DOWNTO 0) <= z;
w(2,2) <= '1';
3. Implement an 4:1 multiplexer called mux_4 with inputs s1:0, d0:3, and output y, using
Xilinx ISE 9.2i tools for Spartan 3E FPGA board. Follow the same steps in previous in
Experiments to synthesize and obtain a timing diagram after simulation to verify correct
outputs.
4. Record your results ( Truth table, VHDL code, RTL, Timing diagram)
Report :
1- Explain the data type used in procedure no. 3.
2- Use 4:1 multiplexer to implement two-input AND gate function.
3- Sketch a schematic of the circuit described by the following HDL code. Simplify the
schematic so that it shows a minimum number of gates.
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--------------------------------------------------------------------------
entity exercise3 is
port ( a, b, c: in STD_LOGIC;
y, z: out STD_LOGIC);
end exercise3;
--------------------------------------------------------------------------
architecture synth of exercise3 is
begin
y <=(a and b and c) or (a and b and (not c)) or (a and (not b) and c);
z <=(a and b) or ((not a) and (not b));
end synth;
--------------------------------------------------------------------------
4- Implement 8:1 multiplexer using 2:1 multiplexers.