Module 3 1

Combinational Circuits Part 1 Lecture and Laboratory

Part 1: Adder and Subtracter

Design Exercises

1. Design a 3-bit ripple carry adder using full adders as building blocks. Include
the carry-in to the LSB.
2. There should be 7 inputs: 3-bit Addend (A2A1A0), another 3-bit Augend
(B2B1B0), and 1- Cin, the carry-in to the LSB of the adder.
3. There should be 4 outputs: the sum (S2S1S0), and the carry (Cout ), the carry-out is
on the MSB. Fill-up the table below 3.1. Demonstrate the result to your respective
instructor
Circuit Diagram:

Authors : Sarmiento, J.; Macabagdal, C.B.; Serrano, R.R.; Magboo, A.

 Module 3 2
Combinational Circuits Part 1 Lecture and Laboratory

Implementation:

Truth Table:

A2 A1 A0 B2 B1 B0 CIN COUT S2 S1 S0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 1 0 1 0 1 0 0 1 1 1
0 1 0 1 0 1 1 1 0 0 0
0 1 0 0 1 0 0 0 1 0 0
0 1 1 0 1 1 0 0 1 1 0
1 0 0 1 0 0 0 1 0 0 0
1 1 1 1 1 1 0 1 1 1 0
1 1 1 1 1 1 1 1 1 1 1
0 0 1 1 1 1 1 1 0 0 1

Tab. 3.1: 3-bit ripple carry adder logic behavior

Authors : Sarmiento, J.; Macabagdal, C.B.; Serrano, R.R.; Magboo, A.

 Laboratory 3

Designing a Combinational Circuits

Design Problems 1

1. Design a 6-bit ripple carry adder using only 3-bit adder blocks like the one in Figure 3.4? (Do
not use individual full adders as building blocks.) Draw the schematic.

Fig. 3.4: 3-bit adder block

Schematic diagram:

6-bit Ripple Carry Adder:

Truth Table:
A0 B 0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 CIN COUT S0 S1 S2 S3 S4 S5
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 1 1 1
0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 0 0 0 0
1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 1 1 1 1 1
1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2. Create a 4-bit ripple carry adder using only 3-bit adders? Hint: use one 3-bit adder for the
least significant 3 bits and use the most significant bit from the other 3-bit adder for the
fourth bit. (Again, do not use individual full adders as building blocks.) Draw the schematic.
SCHEMATIC DIAGRAM:

4-BIT RIPPLE CARRY ADDER:

3. Using your design for the full adder, determine the worst case propagation delay from the
inputs to the carry-out output bit. Assume each gate has the same delay, 1 gate delay.
Schematic diagram of Full Adder:

Since Propagation Delay = Td = 1/2f ,

Propagation Delay from inputs to carry out:

Td = 1/2f
= ½(1000Hz)
=0.5 ms or 0.5x10-3s

4. Using your designs for the full adder and the 3 bit ripple carry adder (Design 3), determine the worst
case propagation delay from the least significant input bit (of either input number A or B) to the
carry-out output bit. Again, assume each gate has the same delay, 1 gate delay.
Schematic diagram of 3 bit-ripple carry Adder:
 Since Propagation Delay = Td = 1/2f ,

Propagation Delay on 1 input of the Full Adder:

Td = 1/2f
= ½(1000Hz)
=0.5 ms or 0.5x10-3s
Propagation Delay from inputs to carry out:
Td = 3(0.5x10-3s)
= 1.5x10-3s
= 1.5ms

Findings and Conclusion:

Part 2: Signed Operations

Design 1: Negation (Two’s Complement)

1. To obtain the negative of any number, we can use only inverters and an adder. Let say the
equation for two’s complement is
−p= p+1 (1) where p is
called the One’s Complement of P and is obtained by inverting each bit of P number and –P
is two’s complement of P number.

1. Design and Test a 4-bit block that gives the negative of any 4-bit input applied to it.
Demonstrate your experiment to your instructor
Design 2: Signed Integer Adder

Design a 4-bit Two’s Complement Adder (i.e. one that adds two 4-bit numbers in Two’s
Complement form), and test it.

Design 3: Signed Integer Subtracter

Construct a circuit for a 4-bit Two’s Complement Subtracter. Test the circuit and document
the result.
 Module 3 9
Combinational Circuits Part 1 Lecture and Laboratory

Part 3: Decoder
Laboratory 4

Gray to Binary Converter

Objective : 1. To realize Gray Code to binary Converter
2. To learn how to generate binary code from gray code
Gray code to Binary Converter
Gray Code Binary Number
G3 B3 B2 B1 B0 G2 G1 G0
0 0 0 0 0 0 0 1
0 0 0 0 1 0 1 0
0 0 0 1 0 0 1 1
0 0 0 1 1 0 1 0
0 0 1 0 0 1 0 0
0 0 1 0 1 1 1 0
0 0 1 1 0 1 1 1
0 0 1 1 1 1 1 0
1 0 0 0 0 0 0 0
1 0 0 0 1 0 0 1
1 0 0 1 0 0 1 1
1 0 0 1 1 0 1 0
1 0 1 0 0 1 0 0
1 0 1 0 1 1 0 1
1 0 1 1 0 1 1 1
1 0 1 1 1 1 1 0

G1
B3B4
00 01 11 10

00 0 0 1 1
B1B2

01 0 0 1 1

11 0 0 1 1
B3 = G3
10 0 0 1 1

G2

B3B4
10
00 01 11 10

00 0 1 0 1
B1B2

01 0 1 0 1

11 0 1 0 1
Authors : Sarmiento, J.; Macabagdal, C.B.; Serrano, R.R.; Magboo, A.
0 1 0 1
 Module 3 10
Combinational Circuits Part 1 Lecture and Laboratory

B3 = G2  G3

Authors : Sarmiento, J.; Macabagdal, C.B.; Serrano, R.R.; Magboo, A.

 Module 3 15
Combinational Circuits Part 1 Lecture and Laboratory

G3

B3B4
00 01 11 10

00 0 1 0 1
B1B2

B3 = G1  G3  G2
01 0 1 0 1

11 1 0 1 0

10 1 0 1 0

G4

B3B4
00 01 11 10

00 0 1 0 1
B1B2

01 1 0 1 0

11 B3 = G1  G3  G2  G0
0 1 0 1

10 1 0 1 0

Gray to Binary using XOR gates

Notes:

Authors : Sarmiento, J.; Macabagdal, C.B.; Serrano, R.R.; Magboo, A.

 Module 3 16
Combinational Circuits Part 1 Lecture and Laboratory

Gray to binary using NAND Gates Only

Authors : Sarmiento, J.; Macabagdal, C.B.; Serrano, R.R.; Magboo, A.